Vivado 2018.3 fails during Implementation with error:
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (17) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 17 sites.
Term: rgb_led_tri_i[0]
Term: rgb_led_tri_i[1]
Term: rgb_led_tri_i[2]
Term: rgb_led_tri_i[3]
Term: rgb_led_tri_i[4]
Term: rgb_led_tri_i[5]
Term: rgb_led_tri_i[6]
Term: rgb_led_tri_i[7]
Term: rgb_led_tri_i[8]
Term: rgb_led_tri_i[9]
Term: rgb_led_tri_i[10]
Term: rgb_led_tri_i[11]
Term: led_4bits_tri_i[0]
Term: led_4bits_tri_i[1]
Term: led_4bits_tri_i[2]
Term: led_4bits_tri_i[3]
Term: and eth_mdio_mdc_mdio_i
Background: This project has been working for a long time using Vivado 2017.4. But now we're moving to Vivado 2018.3 so I upgraded the project and hit this problem.
Searched online and found few similar cases but they all were resolved by getting new board files from Digilent, however I'm using the latest files already (from April 18th 2019).
Can anyone @ Digilent try to reproduce and provide board files qualified for 2018.3 in Arty (ver. C) board?
Question
edge30
Hello,
Vivado 2018.3 fails during Implementation with error:
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (17) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 17 sites.
Term: rgb_led_tri_i[0]
Term: rgb_led_tri_i[1]
Term: rgb_led_tri_i[2]
Term: rgb_led_tri_i[3]
Term: rgb_led_tri_i[4]
Term: rgb_led_tri_i[5]
Term: rgb_led_tri_i[6]
Term: rgb_led_tri_i[7]
Term: rgb_led_tri_i[8]
Term: rgb_led_tri_i[9]
Term: rgb_led_tri_i[10]
Term: rgb_led_tri_i[11]
Term: led_4bits_tri_i[0]
Term: led_4bits_tri_i[1]
Term: led_4bits_tri_i[2]
Term: led_4bits_tri_i[3]
Term: and eth_mdio_mdc_mdio_i
Background: This project has been working for a long time using Vivado 2017.4. But now we're moving to Vivado 2018.3 so I upgraded the project and hit this problem.
I also tried re-making a basic project from scratch completely in 2018.3 but hit the same problem. The basic project was made with the steps in https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start
Searched online and found few similar cases but they all were resolved by getting new board files from Digilent, however I'm using the latest files already (from April 18th 2019).
Can anyone @ Digilent try to reproduce and provide board files qualified for 2018.3 in Arty (ver. C) board?
Thanks
Link to comment
Share on other sites
1 answer to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.