IP not being read correctly

[Antonio Fasano]

Hi,  Guys

I am facing another difficulty with Arty-Z7-20. One of the custom IP´s that I made has only one output (square wave).

I change the output to Output <= ´0´ in the vhdl file using the"Edit IP in Packager" option

Then I re-generate bitstream in the main project after updating the IP.

The resulting bitstream seems to be picking the IP vhdl from somewhere else, because in the resulting design, the square wave signal is still present. (The IP packager shows the correct path to the file, though...)

 It seems that the vhdl for the IPs come from somewhere else. No matter what I change in them, the result remains the same ...  Go figure ... 

Have you ever seen that behaviour ?

Antonio

[jpeyron]

Hi @Antonio Fasano,

Are you able to upgrade ip cores in your project?

reports->report ip status->upgrade ip cores

Please attach a screen shot of your block design and your tcl script.

best regards,

Jon

[Antonio Fasano]

Hi, Jon,

 

I went back to the old computer and VIVADO 2018.1. I did the same change to the IP. Updated the IP and tested the new solution. It worked flawlessly. Then I copied the whole project to the new computer with VIVADO 2018.3 and upgraded the project to 2018.3. Recompiled everything and the new bitstream works OK.

My concern now is if I make any change to the IP in 2018.3, will it get to the resulting bitstream ?

What hints should I look for to know that it has eventually not been processed correctly. Those kinds of problems take days to figure out the solution ...

Is there a short manual where we can find an explanation for the file structure of a VIVADO project ?

Those endless XILINX manuals take months to read and information is not objective in almost all of them ...

Thanks

Antonio

[jpeyron]

Hi @Antonio Fasano,

I am glad to hear that you are able to get a working bitstream in "Vivado 2018.3". Thank you for sharing what you did.  Here is the Arty-Z7 resource center.

We do not have a tutorial that explains the File structure of Vivado projects. I have passes your suggestion on to our content team.

In regards to vivado versions differences I typically look at the known issues for each Vivado version to see what potential issues may occur.  In times past the even versions of Vivado were usually more stable. I believe Xilinx is moving to less versions with each version being fairly stable.

best regards,

Jon