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ZYBO not working with Vivado 2015.4


Ag

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Hi,

I recently purchased a ZYBO board and began testing it using the Digilent getting started tutorials using Vivado 2015.4 Webpack on Windows7.  After meticulously following the tutorials serveral times, and each time with the same result - no errors but board does not respond (no blinking lights, no reponse to buttons), I began to suspect that my ZYBO was defective.  As a last resort, since the tutorials are based on Vivado 2015.1 ("or later"), I created an VirtualBox Windows7 machine and installed Vivado 2015.1 Webpack on it and again went through the tutorials. Using Vivado 2015.1, everything works perfectly.

So here is my question: what do I need to do to use ZYBO board with Vivado 2015.4?   I do not want to work with outdated software.

Any ideas?

 

Thanks in advance for any help!

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Sorry, but my screen shots seem to dissapear when I sumbit, and I am not allowed enough file upload space to provide a document containing the screen shots.  Here are the errors and messages:

[Constraints 18-631] No BOARD_PART_PIN found named 'btns_4bits_tri_i_0. [design_1_axi_gpio_0_0_board.xdc:3] (11 more like this)

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 12 out of 142 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: leds_4bits_tri_o[3:0], btns_4bits_tri_i[3:0], sws_4bits_tri_i[3:0].

[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

Best regards,

Ag


 

 

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Hi Bianca,

I searched the web for MSVCP110.dll and found this https://forums.xilinx.com/t5/Installation-and-Licensing/Vivado-2015-3-uninstall-fails-msvcp110-dll-is-missing/td-p/666152

which solved my problem regarding being unable to de-install Vivado 2015.4.  After de-installing I was able to re-install, and go through the tutorials - lo and behold: flashing lights!:)  After having had all of that fun, I will now go back to the boring tast of reading the book;)

Many thanks and best regards,

AG

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The problem is that i don't know if it will erase every directory without errors, but you could try it and then reinstall. I never tried to simply erase Vivado from the computer without uninstalling. You can give it a shot but I can't guarantee that will solve the issue. Maybe you're lucky and it does.

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Hi Bianca,

It's nice to see that you are still with me on this:)

I searched for MSVCP110.dll on the good machine, and then compared the results against the "bad" machine, but could not find any significant differences.  Anyway, I did a "repair" on both the installed Microsoft Visual C++ 2015 and the installed Microsoft Visual Studio 2015, to no avail.  Taking your advice, I then tried to reinstall Vivado without uninstalling, but the installer refuses to install in the existing directory.  I guess that means I will have to just try deleting the old directories and then try reinstalling.

You agree?

Best regards,

Ag

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Hello Ag,

Your computer is missing the Visual runtime that comes with the installation of  Vivado 2015.4. If you don't have that your application might not work fine (your case) and you cannot uninstall it.

My recommendation for you is to reinstall Vivado 2015.4 without uninstalling and see if will work. If it doesn't, you should try to find the redistributable matching  MSVCP110 . You should find to which one it belongs by searching on google. My belief is that it belongs to Microsoft Visual C++ 2012 but i can't tell if for x64 or for x86. 

Best regards,

Bianca

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Hi all,

I have now confirmed that my 2015.4 installation is indeed defunct.  I logged into another machine and started the Vivado 2015.4 which I had already successfully setup and tested for my ARTY board, went to "Help->add design tools and devices" and added the zync7 devices to the checked boxes to install whatever is needed for the ZYBO, and after successfully adding the devices and restarting Vivado 2015.4, I performed the tutorials with no problems and with the ZYBO working as expected.  I then went back to the problem installation and tried "Help-> add design tools and devices" there, and again got the error message as above (MSVCP110.dll missing).  So that installation obviously was causing the problems.  I may just abandon that installation and use the other machine, or I may look closer into the problem machine to find out just what went wrong.

Thanks to all contributors for the help you have provided.

Best regards,

Ag

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Hi Bianca,

I first tried to de-install using "Xilinx Uninstall 2015.4" in the program menue, then using Windows7 standard de-installation menue, then I tried using "xsetup.exe" in the Xilinx/downloads/Vivado_HL_WebPACK_2015.4 directory, and also in the .Xilinx directory.  In each case I get this error popup message:

 

 

"The program cannot be started, as MSVCP110.dll is missing on the computer. To solve the problem, install the program again."

(My translation of the the German message.)

 

How do I re-install - just delete all relavent directories and hope for the best, or is there a better solution?

Regards,

Ag

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Hi Ag,

I based my design on the getting started tutorial from Digilent:

https://reference.digilentinc.com/zybo:gsg

Although I dislike and mostly advise against multiple tutorials, you might find some help there regarding the adaptation of your project to mine. I have not read the zynq book so I do not know if there are any differences between this tutorial or the other, being a simple project there should be little to no differences in the HDL (Vivado) part of the project. I recommend sticking to the SDK part because that seams to be working.

Good Luck.... and my the odds be ever in your favor 

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1. It should work , I currently have ISE 14.7, VIvado 2014.3, VIvado 2014.4, VIvado 2015.1 and VIvado 2015.4 installed so Xilinx products will probably not cause any issues among themselves. The only issues which I have experienced so far from having so many versions of Vivado installed is a drastic lose of hard-disk space, every version is approx 20 GB and a problem with the environment variable, which is mostly used to determine the "default"(for a lack of a better word) version of Vivado you are currently using.

2. If you follow the tutorial from the zynqbook you aren't doing anything wrong. Most likely there is something wrong with your vivado installation, or the board package. This is also verified by the fact that the project from kypropex generates errors.

3.  TCC0_WAVEx_OUT,  SDIO_0,  USBIND are ports of the zynq processor which maybe connected to the FPGA part of the zynq. They are set and configured inside the processing_system, because you are a novice at this I strongly recommend you ignore them for the time being, or else you might get into complications and loose sight of your current project.   

Try a clean reinstall, and then redo the project from zero.

Best regards,

Ciprian

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Hi Bianca,

Thanks again. Also, because the second tutorial works fine, I am confident that the ZYBO board files are properly installed (and were sourced as per Ciprian´s link), and I therfore too began to suspect the 2015.4 installation. Before re-installing Vivado, I would like to be clear on a few issues:

1. My 2015.1 installation is on a freshly installed Windows7 virtual machine.  My 2015.4 installation is on the same host where the VM is installed, and it already had Xilinx ISE 14.7 installed.  Is it OK to install Vivado 2015 on same system together with ISE 14.7?

2. When testing the project from kypropex, I do the following: start Vivado 2015.4, click "Open Project", navigate to subfolder "LED_test" found in his downloaded directory, click the LED_test Vivado Project File, then click OK. After the project loads, I "Open Block Design" and then click "Validate Design".  It validates with no errors or warnings. Then, I start "Generate Bitstream" and the critical messages and errors occur.  Am I doing something wrong?  Why do my tutorials show no errors or warnings?

3. I notice that in the tutorial screenshot and in the project from kypropex, the processing_system7_0 displays 3 unconnected TCC0_WAVEx_OUT connections, an unconnected SDIO_0 and an unconnected USBIND which do not appear when I add the IP.  I tried re-customizing the IP in alignment with Kypropex's custom IP, but I am not able to get the GPIO MIO pins set in alignment (the green/gray activation status of each pin). I also noticed that "QUAD SPI Flash" is set on his and was not set on mine. Can you exlain where these settings are originating (apparently not from the board files)?

As an added note, I loaded the bitfile from kypropex's project as Ciprian suggested, and the ZYBO LEDs flash as they should.

Best regards,

Ag

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As an addition to what Ciprian said because you can use 2015.1 without any problems, please try to reinstall Vivado 2015.4. It might be possible to be some problems from installation. Put again the board files and make an update to the driver cables (if necessary). 

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Hello Ag,

I downloaded the "reference design" which was uploaded by kypropex. I took the board support files from the Digilent website (https://reference.digilentinc.com/vivado:boardfiles2015) and copied the zybo file in to D:\Xilinx\Vivado\2015.4\data\boards\board_files, this is because I installed Vivado on drive D:\. The validation of his design was success full and so was the bit generation. I retried this with the board files which you uploaded and I didn't get an error when validating project and generating the bit. Make sure that the board files are in the correct folder D:\Xilinx\Vivado\2015.4\data\boards\board_files\zybo\B.3. The good news is that as far as I can tell you are right, there is something wrong with the identification of the board files.

Just to make sure that the board is functioning correctly; the SDK project from kypropex, has a valid bit file(which was probably exported by him), try to program that file along with the elf file in to the FPGA from SDK 2015.4. This is covered on page 32 of the zynqbook. 

Ciprian

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Hi kypropex,

Thank you helping out on this issue.

" First of I don't particularly understand where you have gotten your sources from, they seam to be a combination between several tutorials; I would recommend, choosing one tutorial and sticking to it and if it dose not work search for a new one (this is assuming I am right). "

Actually, I am going through "The Zync Book" from start to finish and am using "The Zync Book Tutorials" downloaded from the link referenced in the bootk, so I am being consistent in that I am using one tutorial source.  The first tutorial does not work for me, the second one does.

" What is missing from the log is the programming of the .elf file (this is the compiled C project which you have written in SDK)  to the board, this is a bit peculiar because the processor has been reset and configured, which usually happens when the elf is written (as far as I know). In order to program the .elf file on the Zybo board you have to right click on the project -> Run As -> Lunch on Hardware (System Debugger) (please refer to attachment 1 of this message). "

The tutorial says to use Run As -> Lunch on Hardware (GDB), which I did.  That explains why you did not see the .elf log entry, which is apparantly supressed with GDB. I re-ran as  Lunch on Hardware (System Debugger) and thereby do see the .elf log entries. Nevertheless, the ZYBO does not respond.

4 hours ago, kypropex said:

If none of this has been any help so far, I'll also attache a link to the project I have written In Vivado 2015.4 to test your .c file. The project works for me, on a Zybo board. I suggest you look it over and compare your project with mine.

I closed my tutorial project in Vivado and then opened the project you provided. Upon doing a "validate Design" I get 12 critical messages and 3 errors (see screen shot below).

As a novice, I am guessing that we have different ZYBO board files being loaded.  Your project obviously does not work for me. I again followed the instructions in the Zync Book tutorial for downloading and installing the board files. Here is how my directories look (files added as attachment):

Can you make any sense of the above?

Thanks again for any help.

board_files.zip

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Hi Ag,

First of I don't particularly understand where you have gotten your sources from, they seam to be a combination between several tutorials; I would recommend, choosing one tutorial and sticking to it and if it dose not work search for a new one (this is assuming I am right).

The second issue is that I do not understand what is wrong, the board seams to be programmed correctly with the .bit file (this is basically the "compiled" version of what you did in Vivado) therefore the JTAG chain is initialized and the board has been identified. What is missing from the log is the programming of the .elf file (this is the compiled C project which you have written in SDK)  to the board, this is a bit peculiar because the processor has been reset and configured, which usually happens when the elf is written (as far as I know). In order to program the .elf file on the Zybo board you have to right click on the project -> Run As -> Lunch on Hardware (System Debugger) (please refer to attachment 1 of this message). This is assuming you have not already done this.

If none of this has been any help so far, I'll also attache a link to the project I have written In Vivado 2015.4 to test your .c file. The project works for me, on a Zybo board. I suggest you look it over and compare your project with mine.

https://www.dropbox.com/s/tm6hv5b5pmct3za/LED_VIVADO_215_4.zip?dl=0

I'm curious about the answer to your problem, so please reply here if you have found the soulion to your problem.

Best regards.     

prog_elf.png

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Hi Bianca,

Sorry to have to come back on this, but it seems I still have a problem.  My ZYBO works with Vivado 2015.4 when I go through tutorial for "C:\Zync_Book\sources\zybo\zynq_interrupts\interrupt_counter_tut_2B.c", but when I try tutorial for "C:\Zync_Book\sources\zybo\first_zynq_design\LED_test_tut_1C.c" I again get no errors, but no response from the ZYBO.  The DONE LED lights up green, the ZYBO does appear in the "View Target Connection" "JTAG Device Chain" before and after "Run as -> Launch on Hardware (GDB) (see screen shot below).  I already tried again re-installing the cable drivers, but that does not help with this tutorial - no lights flashin after launch.  I reconfirmed that this tutorial does work under 2015.1 (LEDs flash in the expected pattern).

I first suspected a clock problem (see 2nd screen shot), but this looks the same in Vivado 2015.1, which does work.

Here is the output from SDK.log:

17:50:44 INFO  : Launching XSDB server: xsdb.bat C:/Xilinx/SDK/2015.4/scripts/xsdb/xsdb/xsdb-server.tcl
17:50:47 INFO  : XSDB server has started successfully.
17:50:57 INFO  : Processing command line option -hwspec C:/Zync_Book/first_zync_design/first_zync_design.sdk/first_zync_system_wrapper.hdf.
17:51:00 INFO  : Checking for hwspec changes in the project first_zync_system_wrapper_hw_platform_0.
17:51:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:51:49 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:51:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo 210279772245A" && level==0} -index 1' command is executed.
17:51:50 INFO  : FPGA configured successfully with bitstream "C:/Zync_Book/first_zync_design/first_zync_design.sdk/first_zync_system_wrapper_hw_platform_0/first_zync_system_wrapper.bit"
17:52:22 INFO  : ps7_init is completed.
17:52:22 INFO  : ps7_post_config is completed.
17:52:23 INFO  : Processor reset is completed for ps7_cortexa9_0

So now again I am stuck. Can you give me some futher advice?

Many thanks for any help you can provide.

 

 

 

 

screenshots.docx

screenshots2.docx

LED_test_tut_1C.c

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I'm glad it worked.

Since you couldn't see the JTAG chain in the hardware manager, the board was not programmed correctly because Vivado couldn't see your board.  Once you installed the drivers the program recognized it and from now on you should not have any problems. Have fun with your Zybo!

Best regards,

Bianca

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Hi Bianca,

Thank you for your continued support.

To clear, my ZYBO board works perfectly when using Vivado 2015.1 (or perhaps better stated, using Xilinx SDK 2015.1, since the problem first makes itself apparent in SDK).  I only have this issue when using Vivado/SDK 2015.4.

I assume the board gets programmed, since the SDK log states that "FPGA configured successfully with bitstream "C:/Zync_Book/.....", and the DONE light on the board lights up green immiatly upon the completion notification.

I don't see a JTAG chain appearing in the hardware manager, and the board appears as USB serial com port COM3 in the window's device manager.

As you suggested, I perfomed an update to the cable drivers.  That apparantly fixed the problem, since the ZYBO is now performing as expected also in Version 2015.4, so for me the issue is not solved.

Thank you for your great support!  Is there someway that I can give you points?

 

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Ok, first of all, stick to the board files. Second, you said that your board doesn't work. You can't see leds light nor the buttons and switches are working, so I have a few other questions for you

1. Are you sure that the board was programmed? Did the DONE led (LD10) light up?

2. When you program the FPGA does the JTAG chain appear in the hardware manager? If no, does you board appear like serial com in the windows's device manager?

Also you can make an update to your cable drivers. in order to do that you should go to the following path: C:\Xilinx\Vivado\2015.4\data\xicom\cable_drivers\nt64 and install intstall_drivers.exe . 

Let me know how this works.

  

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Hi Bianca,

Thank you for your response.

I did indeed copy the board files into the new version of Vivado (C:\Xilinx\...\data\board\board_files\, and also the subdirectory "zybo" additionally copied to ...\board\board_parts\ zync\ as instructed in "The Zync Book" tutorial). I did this the same in both versions 2015.1 and 2015.4.

Following your suggestion, I just tried selecting the FPGA manually, not using the board files.  Doing it that way and otherwise following the tutorial, I do not get the option to "Select Board Part Interface" to associate the leds_4bits to the axi_gpio_0 output port in the dialog when running the "Connecton Automation" link. The area under "Options" is completely blank.  At that point I am stuck, since I  now have no LEDs defined in the block design.

Can you give me some further assistance?

Many thanks.

 

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Hello Ag,

From what I see here you are using the board files for your Zybo. Did you copy the board files into the new version of Vivado? Also, Have you tried selecting the FPGA manually, not using the board files? If not, please try it this way and see with a simple blinking leds project if the board is working. Let me know what you find.

Best regards,

Bianca

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Hi curtoid,

I thank you for your response, but it appears to me that my issue is unrelated.  I cannot even get the simple tutorial which just blinks the 4 LEDs to work with Vivado 2015.4, and there is no code included there regarding audio initialization.  Also, the link which you referenced is dating back to Vivado 2014.x whereas my ZYBO is working fine with Vivado 2015.1. I am a newbie regarding this environment and maybe I am missing something, but it seems to me that either the ZYBO board files need to be updated to match the new Vivado version, or the new Vivado version is in some way defunct, at least in regard to ZYBO. I am not sure how to address this. I feel like I am stuck between Digilent and Xilinx as to who is at fault and therefore to whom to address the problem. expecting each to respond saying the problem belongs to the other.  In any case, my issue is still unsolved.

In the meantime I will plug along using the 2015.1 version until I have learned how to follow the program steps in a debugger and hope to find insight as to how to correct the problem or am able at least to better localize and define the problem area more specifically.

 

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I just am getting started with this as well, but I was able to figure out one issue - the I2S AXI for the Audio is not configured correctly if the IP is updated. It will lock up the system during initialization. I was trying to get the zybo_base_system project up and running. At first, I commented out the audio initialization at the beginning of main() and then didn't run that part of the demo and everything else worked fine. Afterward, I went back to the block design and replaced the AXI_I2S_ADI_1 IP with a new one and replaced every connection and deleted the old one, assigned the correct name to it and also the correct address. There may be an easier way to fix it, but it worked.

 

I got the idea to do that from this thread:

 

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