Pmod DA3 clocking

[Ahmed Alfadhel]

Hi @jpeyron, 

Kindly see the attached picture.

I have the following clocking options:

MIG_7series/ui_clk :83 MHz

clk_wiz_0/clk_out_1 : 166 MHz

And I want to feed my Pmod DA3 with the desired clocking rate. But I don't know what to choose from these clocks?

So could you help me in choosing the right clock for the two pin of Pmod DA3 ?

Thanks .

[jpeyron]

Hi @Ahmed Alfadhel,

Looking at the Datasheet for the AD5541A here.The AD5541A operates at clock rates of up to 50 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.  I believe the highest frequency would be 50 MHZ for the ext_spi_clk.  Its my understanding that we use the MIG_7series/ui_clk :83 MHz clock due to issues relating to the MIG/DDR.  I would also suggest looking at the AXI Quad SPI v3.2 LogiCORE IP Product Guide.

thank you,

Jon

[Ahmed Alfadhel]

Hi @jpeyron,

In order to specify the required clock of each ext_spi_clk and s_axi_aclk , I need to know the SPI mode of Pmod DA3 IP core .

According to PG153 ( AXI Quad SPI v3.2 LogiCORE IP Product Guide) page 15 there are different modes of operations for SPI protocol.

Looking forward your reply.

Thanks in advance.

[jpeyron]

Hi @Ahmed Alfadhel,

 In section 2 Interfacing with the Pmod on page 1 of the reference manual for the Pmod DA3 here it states the pmod should use spi mode 0.

thank you,

Jon

[Ahmed Alfadhel]

Hi @jpeyron,

Kindly, Mode 0 stands for what ?

Thanks.

[jpeyron]

 

Hi @Ahmed Alfadhel,

Here and here are good descriptions for the  spi (Serial Peripheral Interface) and the spi modes. 

thank you,

Jon

 

[Ahmed Alfadhel]

Hi @jpeyron,

I want to know :  Pmod DA3 IP core with which mode was designed ? 

does it Legacy mode, Enhanced mode, or XIP mode?

Thanks.

[jpeyron]

Hi @Ahmed Alfadhel,

I have reached out to our content team about your Legacy, Enhanced or XIP mode question.  If I were guessing i would say that its the Enhanced mode since the interface is set to AXI4 but I am not sure. 

thank you,

Jon

[Ahmed Alfadhel]

Thanks @jpeyron, because you contacted your team for me. I am waiting to their response. 

By the way, you said :

6 minutes ago, jpeyron said:

since the interface is set to AXI4

there is no AXI4 in Pmod DA3 IP core ! As I can see it is AXI_Lite_SPI buses.

Thanks again.

[Ahmed Alfadhel]

Hi @jpeyron,

I connected each of ext_spi_clk and s_axi_aclk to 50 MHz clock . But when I visualized the SCLK signal on my oscilloscope, it was only 3.13 MHz ! Why ?

Kindly, see the attached pictures.

Thanks . 

 

[kwilber]

If you look in the PmodDA3_axi_quad_spi_0_0.xci you will see that it is using a sck_ratio of 16.

 

In the AXI Quad SPI reference manual you will find

and

 

With your 50 Mhz clock, 50 Mhz / 16 = 3.125 Mhz.

[jpeyron]

Hi @Ahmed Alfadhel,

@kwilber is correct.

I heard back from our content team. My guess was incorrect. We are using AXI4 Lite so it's definitely not XIP mode, since there is a "MODELPARAM_VALUE.C_XIP_MODE" parameter in the XCI files that is set to 0. They are under the understanding that we are using Legacy Mode .

thank yo,u

Jon

 

 

[Ahmed Alfadhel]

Hi @jpeyron,

According to the selection of 50 MHz as a clock signal for both ext_spi_clk and s_axi_aclk ,  then we have  synchromous clocking for these two signals. 

Then the value of Async_Clk must be set to 0 . But I found in PmodDA3_axi_quad_spi_0_0.xci  the property Async_Clk was set to 1 (not a default value !) on line 83 and 106 .

Looking forward your reply .

Thanks in advance.

[jpeyron]

Hi @Ahmed Alfadhel,

Can you please attach the main.c, PmodDA3.c and PmodDA3.h you are using.

thank you,

Jon

[Ahmed Alfadhel]

Hi @jpeyron,

Kindly find the attached files.

Kind Regards.

testperiph.c

PmodDA3.h

PmodDA3.c

[kwilber]

It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits. 

[kwilber]

The address bits being sent should not pose a problem since ~LDAC gets pulled low after the data bits have been sent and that will transfer the last 16 bits clocked into the serial register to the DAC.

Admittedly, since the chip doesn't use the address bits, it is wasted time.

That is one of the cons when using third party IP - generality usually costs either performance or resources.

If you run into performance limitations, you would then consider coming up with your own logic for talking to the chip. In this case, the protocol is fairly simple. 

[jpeyron]

Hi @Ahmed Alfadhel,

In the testperiph.c the DemoInitialize() needs to be at the top of main. You need to have a function prototype for DemoInitialize()  as well.  I would also suggest making your main.c easier to use.  Something similar to the attached pmodda3_main.c below. You will need to create the function DA3_WritePhysicalValue. Use the PmodDA1.c and PmodDA1.h as reference. 

thank you,

Jon

pmodda3_main.c

[Ahmed Alfadhel]

11 minutes ago, kwilber said:

If you run into performance limitations, you would then consider coming up with your own logic for talking to the chip. In this case, the protocol is fairly simple. 

Hi @kwilber,

Do you mean I have to build my own IP core for Pmod DA3 using Vivado IDE , like that of Hamester ?

[Ahmed Alfadhel]

Hi @jpeyron,

21 minutes ago, jpeyron said:

pmodda3_main.c

did you test this Pmod (DA3) with the above piece of code previously? Or I am going the first one to test it using the IP core you gave me ?

I want to know what is I am doing . Working with a validated third IP core or I am just testing some IP core that was built roughly ?

Thanks.

[kwilber]

You may not have to build your own.

That becomes a design decision that only you can make based on the requirements/specifications your design must meet.

If the performance you are getting out of the Digilent IP meets your requirements, there is no reason to roll your own.

On the other hand, if you are not able to meet your requirements and you are running up against limitations of the IP, then either look for a more performant IP or consider designing purpose specific logic.

According to your measurements, it takes 40 bits sent at a rate of 3.125 Mhz for each update of the DAC. That is at least 12.8 microseconds per update. Take the inverse of that and you have a maximum update rate of 78,125 updates/second. Is that sufficient for your design?

[jpeyron]

Hi @Ahmed Alfadhel,

We have not had the bandwidth to create an IP core for the PmodDA3 as mentioned when I posted the generic SPI IP core Named PmodDA3. This IP core facilitates the usage of the pmod ports along with constraints so as all you should have to do is alter the PmodDA3.c PmodDA3.h and create a main.c. The PmodDA3_main.c is not validated. It would be the first draft when starting to create the custom functions needed to send desired output. 

thank you,

Jon 

[Ahmed Alfadhel]

Hi @jpeyron,

I found in PmodDA3_axi_quad_spi_0_0.xci  the property C_NUM_TRANSFER_BITS ( Transaction Width) was set to 8 bits (the default value) on line 90 and 112. I think it must be set to 16 bits, since the Pmod DA3 its resolution is 16 bits. 

Looking forward your reply.

Thanks in advance.