Hello! I have a critical warning message after executing RTL ANALYSIS(Open Elaborated Design) for a simple test design in Zybo board as follows:
[Vivado 12-1411] Cannot set LOC property of ports, Terminal btn[3] cannot be placed on Y16 (IOB_X0Y36) because the pad is already occupied by terminal led[3] possibly due to user constraint ["Q:/Work/CSE4178_Labs/3bit_TFF_v01_src/Zybo-Master.xdc":23]
However when I implement the design and download it to the Zybo, it works without any problem.
Would you please explain to me what is the reason of the above warning message? Thank you in advance.
The xdc file i am using contains the following information(I just use as downloaded with commented out) :
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npcnpc
Hello! I have a critical warning message after executing RTL ANALYSIS(Open Elaborated Design) for a simple test design in Zybo board as follows:
[Vivado 12-1411] Cannot set LOC property of ports, Terminal btn[3] cannot be placed on Y16 (IOB_X0Y36) because the pad is already occupied by terminal led[3] possibly due to user constraint ["Q:/Work/CSE4178_Labs/3bit_TFF_v01_src/Zybo-Master.xdc":23]
However when I implement the design and download it to the Zybo, it works without any problem.
Would you please explain to me what is the reason of the above warning message? Thank you in advance.
The xdc file i am using contains the following information(I just use as downloaded with commented out) :
##Clock signal
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
##Buttons
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2
set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3
##LEDs
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
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