NEXYS III SPARTAN 6 FPGA _Clock Input Issue

[ANBARASU]

Hi All,

  I am using the Nexys III SPARTAN 6 FPGA Board along with VmodMIB 68 Pin VHDCI adapter board for Image Sensor OV10635  data processing.

I have configured the EXP-IO9_P pin as output clock 20MHz to be connected to Image sensor input pin & I am measuring the Image sensor Pixel clock output to EXP-IO10_P by using this pin.

During measurement i can able to see the FPGA Output as 20MHz in FPGA board and as well at the  Image sensor board side. 

But the issue is when i am connecting the Image sensor Pixel clock output to FPGA Pins the clock frequency is varying . I need to measure 20MHz at the FPGA input side , but i am measuring  more than 30MHz and Amplitude variation around 0.4mV with Input amplitude level.

But during the measurement at the Image sensor output side i can able to see the 20MHz , when i am connecting the clock to FPGA it's changing the clock frequency .So could you please tell me what will be the issue ?

 

Note: I am configuring the clock lines as single ended and connecting through external multi strand wires .

[jpeyron]

Hi @ANBARASU,

Please share your ucf file.  Here is the Nexys 3 resource center which has the master ucf file. From my understanding, the VmodMIB is essentially just a break-out board. It doesn't perform any particular function beyond that. All of the material we have available for the VmodMIB can be found on the resource center here. Could you link the datasheet you are using for the  OV10635.

thank you,

Jon

 

 

[ANBARASU]

Hi Jon,

  Thanks for your reply!

Unfortunately the OV10635 Datasheet I can't able to share due to NDA Issue .If I need to share the datasheet OVT should signed NDA with Digilent . Mean time please let me know what is the information your looking in the OV10635 datasheet  

Attached the ucf file for your reference and we are giving the External Pixel clock in below mentioned specification,

Time period is  “40 ns” / Frequency is  20MHz and Duty cycle is 50%.

Regards,

Anbarasu S

Nexys3_master12.ucf

[jpeyron]

Hi @ANBARASU,

Have you checked to make sure that the External Pixel CLK is connect to the correct pin on the OV10635. Does the OV10635 generate its own internal clock?

 cheers,

Jon

[ANBARASU]

Hi Jon,

   Yes the Pixel clock is Generated by OV10635 .I am ensuring the pin connection number between OV10635 & FPGA Board.

Do you have any recommendation for clock line series termination Resistor between OV10635 & FPGA?

Since the clock is main input and output of Image sensor & the flow will be as like below,

FPGA--> 24MHz Clock Generation ---> Connected to OV10635 Input Clock Pin

OV10635--> Generates the 21MHz clock --> Giving Input to FPGA as a Input clock for Data Lines.

Any Recommendation for Nexys 3 Ground & Chassis Termination to my Sensor Unit side?

Thanks & Regards,

Anbarasu S

[jpeyron]

Hi @ANBARASU,

We have not work with or have the OV10635.  We would not have an official recommendation for clock line series termination resistor or the gnd & chassis termination. You could look at schematics and reference manuals of the Zybo Z7 and the PCAM-5C and see if there is any useful information for your project. 

 cheers,

Jon