From a while I am trying to find a way to simulate the xadc and i have not found a proper way and hence I tried again and here is the status
here is my block diagram, here is my project manager pic
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC
);
end component design_1;
begin
design_1_i: component design_1
port map (
dclk_in => dclk_in,
vn_in => vn_in,
vp_in => vp_in
);
end STRUCTURE;
and here is my testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity XADC_test_tb is
-- Port ( );
end XADC_test_tb;
architecture Behavioral of XADC_test_tb is
component design_1_xadc_wiz_0_0
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC);
end component;
signal eoc : STD_LOGIC ;
constant clk_period : time := 0.1ns;
begin
uut: design_1_xadc_0_0 port map(
dclk_in => dclk_in,
vp_in => vp_in,
vn_in => vn_in
);
clk: process
begin
dclk_in <= '0';
wait for clk_period/2;
dclk_in <= '1';
wait for clk_period/2;
end process;
end Behavioral;
here is my log
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity XADC_test_tb
ERROR: [VRFC 10-91] design_1_xadc_0_0 is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:51]
ERROR: [VRFC 10-91] dclk_in is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:58]
ERROR: [VRFC 10-91] dclk_in is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:60]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:38]
INFO: [VRFC 10-240] VHDL file E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.sim/sim_1/behav/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
please someone help me out here. I have various permutation combination to try declare the not declared and I fail every time.
Question
Newbiee
Hi guys,
From a while I am trying to find a way to simulate the xadc and i have not found a proper way and hence I tried again and here is the status
here is my block diagram, here is my project manager pic
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC
);
end component design_1;
begin
design_1_i: component design_1
port map (
dclk_in => dclk_in,
vn_in => vn_in,
vp_in => vp_in
);
end STRUCTURE;
and here is my testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity XADC_test_tb is
-- Port ( );
end XADC_test_tb;
architecture Behavioral of XADC_test_tb is
component design_1_xadc_wiz_0_0
port (
dclk_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC);
end component;
signal eoc : STD_LOGIC ;
constant clk_period : time := 0.1ns;
begin
uut: design_1_xadc_0_0 port map(
dclk_in => dclk_in,
vp_in => vp_in,
vn_in => vn_in
);
clk: process
begin
dclk_in <= '0';
wait for clk_period/2;
dclk_in <= '1';
wait for clk_period/2;
end process;
end Behavioral;
here is my log
INFO: [VRFC 10-163] Analyzing VHDL file "E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity XADC_test_tb
ERROR: [VRFC 10-91] design_1_xadc_0_0 is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:51]
ERROR: [VRFC 10-91] dclk_in is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:58]
ERROR: [VRFC 10-91] dclk_in is not declared [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:60]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd:38]
INFO: [VRFC 10-240] VHDL file E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.srcs/sim_1/imports/new/XADC_test_tb.vhd ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.sim/sim_1/behav/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'E:/Xilinx_new/the_mission/level_2/GO_5/XADC_test/XADC_test.sim/sim_1/behav/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
please someone help me out here. I have various permutation combination to try declare the not declared and I fail every time.
what am i doing wrong here?
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