How to enable CFGMCLK in STARTUP_SPARTAN6 port while in simulation?

[S.D. Chiou]

The [STARTUP_SPARTAN6] port is used in my design. It is described as following:

 

 

/*******************************/
 STARTUP_SPARTAN6 STARTUP_SPARTAN6_inst (
      .CFGCLK (),       // 1-bit output: Configuration logic main clock output.
      .CFGMCLK (i_osc_clk),     // 1-bit output: Configuration internal oscillator clock output.
      .EOS (),             // 1-bit output: Active high output signal indicates the End Of Configuration.
      .CLK (1'b0),             // 1-bit input: User startup-clock input
      .GSR (1'b0),             // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
      .GTS (1'b0),             // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
      .KEYCLEARB (1'b0)  // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
   );
 
BUFG u_su_bufg
(
   .I          (i_osc_clk),
   .O          (int_osc)
);
/*******************************/

 

 

The "int_osc" is used to trig a lot of logic function in my design, and it is proved that the "int_osc" exists in actually implimentation --- due to the logic functions work as desired.

In simulation, however, some logic functions do not work currently as desired, and it seems that the "int_osc" is always a constant, but not a clock.

Because the "int_osc" is not a input port, I can not generate it by verilog code in test bench file.

What could I do to fix the fault in simulation, please?

[jpeyron]

Hi @S.D. Chiou,

I do not have experience using the startup_spartan6 port. Here is the Spartan-6 Libraries Guide for HDL Design that has HDL code for using the STARTUP_SPARTAN6 .  Here is Xilinx SDK code and the Spartan-6 FPGA Configuration User Guide that should be helpful.

thank you,

Jon