Adding VHDL code to block diagram

[goli12]

Hi all,

I have successfully tested my AES encryption core on a Pynq-Z1 using the 125 MHz clock located on pin H16. My next step is to use a PLL in the PS to test the core in the PL with higher clock frequencies.

However, it seems I am not able to add the module to the block diagram as it says that the RTL is an incompatible module. I have also tried Add module to block design,  but that option is greyed-out.

The source file including the Vivado 2018.1 project can be found here.

I appreciate any help :)

Cheers

goli12

[goli12]

Hi @jpeyron

A quick follow up from my previous reply, it looks like Vivado doesn't like adding a module into a block diagram within an RTL project.

To solve this issue, I followed Xilinx's video on how to reference RTL here.

I guess when adding a RTL module into a block design, a new project needs to be created and the RTL code imported.

Cheers for the help!

goli12

[jpeyron]

Hi @goli12,

Here is a forum thread that discusses a similar issue. You might need to re-install Vivado. Could you attach screen shots of your block design when trying to add a module. Are you using the Arty-Z7-20 board file with your project? Here is a tutorial on installing the digilent board files.

thank you,

Jon

[goli12]

 

Hi @jpeyron

 

I have installed Vivado 2018.2 and imported the project which has the same issue.

I am currently using xc7z020clg400-1 part. Changing the board file to the Arty-Z7-20 still does not allow me to add the module.

I have also disabled the constraints file in case if it is conflicting with the procedure.

Shown below is a screenshot of the block design and the "Add Module" box.

Cheers

 

 

[jpeyron]

Hi @goli12,

Once you have the HDL code done you can add a module readily. Here is a forum thread that deals with using the add a module function. I have also attached a few screen shots with using the add a module function. To get the vhdl code to be available in the add a module function i had to add the vhdl code to the sources in the project.

cheers,

Jon