Related to fifo generatior data read and write operation

[aiswarya]

Hello everyone,

i attached  block diagram ..

 

I want to send  32 bit data  from PS to  FIFO GENERATOR in PL.then my custom slave ip will read data  from fifo generator .here is the flow.

 

 

during creation of block  design i faced some problem which i mentioned in below

1)FIFO generator does not have any address so i create and add custom master slave ip (master_slave_ip_0) for data go into FIFO from S-AXI port via my_master_slave_ip address.

 

but my data doesn't  flow from my master ip to FIFO generator..is that block diagram is correct? i didn't add any read and write logic into my_master _slave_ip..

 

 

Thanks and Regards

Aishwarya

 

[jpeyron]

Hi @aiswarya,

I have reached out to a co-worker about your thread. 

thank you,

Jon

[dpaul]

@aiswarya,

Quote

FIFO generator does not have any address so i create and add custom master slave ip (master_slave_ip_0) for data go into FIFO from S-AXI port via my_master_slave_ip address.

A a normal FIFO is not meant to have an address. A write cmd writes into the FIFO an the read cmd reads out from the FIFO. In the axi fifo all this complexity is handled by the axi logic wrappers that come embedded within the fifo IP.

Quote

but my data doesn't  flow from my master ip to FIFO generator..is that block diagram is correct?

Are you running a sim? You should!

In sim, you should be able to see fifo writes when a write axi cmd is issued on the S_AXI side and a read cmd issued on the M_AXI side should empty the FIFO.You should also be able to see where the problem is occurring in your datapath.

 

 

[jpeyron]

Hi @aiswarya,

Sorry for the late reply,  have you tried a different xilinx IP for axi fifo such as the AXI4-Stream FIFO v4.1 LogiCORE IP Product Guide?

thank you,

Jon