We have bought a Arty S7-50 board for a research project to control CMOS sensor with FPGA (Spartan-7, XC7S50). This board has three connectors (J1, J2, J5) to connect FPGA pins on the Arty-S7-50 board to the CMOS pins on our in-house built board. The "Arty S7 Schematic (Rev. E)" provide only definitions of J1 connector's pins of A0 to A5 to FPGA pin, but not A6 to A9. Similarly, the definitions of J2 and J5's pins of IO37 to IO39 are missing.
In summary, we need Digilent Tech support to provide the definitions of J1 connector's pins of A6 to A9 and J2 and J5's pins of IO37 to IO39. So we can find out how these pins are supposed to connect our CMOS sensor pins to those of FPGA.
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We have bought a Arty S7-50 board for a research project to control CMOS sensor with FPGA (Spartan-7, XC7S50). This board has three connectors (J1, J2, J5) to connect FPGA pins on the Arty-S7-50 board to the CMOS pins on our in-house built board. The "Arty S7 Schematic (Rev. E)" provide only definitions of J1 connector's pins of A0 to A5 to FPGA pin, but not A6 to A9. Similarly, the definitions of J2 and J5's pins of IO37 to IO39 are missing.
In summary, we need Digilent Tech support to provide the definitions of J1 connector's pins of A6 to A9 and J2 and J5's pins of IO37 to IO39. So we can find out how these pins are supposed to connect our CMOS sensor pins to those of FPGA.
Arty S7-50 connector pin definition.pdf
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