Difficulty using XADC channel sequencer while in DRP mode with Arty z7

[cfsterpka]

Hi - I've been trying to implement a design based on the XADC demo for the Arty z7-10, but I've been having difficulty figuring out exactly how to properly switch between 3 channels (VP/VN, A0 and A1) when in DRP mode with the channel sequencer.  I've attempted to use the switches to alternate channels as in the example design, though what I would ultimately like to do is poll each channel at a regular timed interval.  Attached are my modifications to the example verilog source and XDC file, any help would be greatly appreciated.

-Chris

Artyz7_mod.xdc

Artyz7_mod.v

[jpeyron]

Hi @cfsterpka,

I do not believe you need this if statement 

 if (sw > 9)
                bad_address <= 1;
            else
                bad_address <= 0;
        end 

these cases are handled by the default case. What errors are you getting with your project? I spent a couple of minutes and I believe I edited the original demo to work with more channels(not tested or checked for errors) and attached bellow.

thank you,

Jon 

xadc_arty_z7_10.v

[cfsterpka]

Thank you for your response jpeyron.  I guess I'm a bit confused how to use the channel sequencer.   When I use your code, it seems that the ADC responds to the differential channels  Vp/Vn, A6/A7, and A8/A9 all simultaneously.  What I am attempting to do is have one channel active (such as Vp/Vn), but then be able switch between Vp/Vn, A0 and A1 programmatically.

[jpeyron]

Hi @cfsterpka,

Tomorrow, i will look into the code i posted to see if i can get it working with the switches.

thank you,

Jon

[cfsterpka]

Hi @jpeyron,

So I've done a few more tests:

1) We have a second Arty z7-10, and I can confirm that the same behavior is happening with that board (all three differential channels seem to be active at the same time).

2) I ran the XADC demo on an Arty S7-50 and it behaved as expected, the switches would activate only one channel at a time. 

Could this be a bug with the XADC demo for the z7 or the channel sequencer?

 

Additionally, I posted this question in Xilinx forums and got the suggestion of attaching the ila and looking at the output of the channels and eoc to see if there are any inconsistencies, so I am currently working on that.

[cfsterpka]

Hi again @jpeyron,

So I'm still having weird issues with this board.  I really need at least 3 active ADCs for my project, but at best I can only get 2 channels active (Vp/Vn and A0) without interference from other channels.  Is there a mistake I'm making or is this board not working properly?

[xc6lx45]

Hi,

are you aware that the chip has only two physical AD converters, plus analog multiplexers to feed them from a larger number of inputs? This is where the sequencer comes in.

[cfsterpka]

Thanks @xc6lx45,

 

Yes, I am aware of this.  What's confusing to me is that when I attempt to use the DRP to select a single channel, several seem to all be active at at the same time.