Reading a variable from Verilog IP

[vishav]

Hi,

I have to design a counter IP which measures the number of positive edges on a signal. I was following the tutorial from digilent which is given on this link:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start

The tutorial mentions the user logic as given below. The Verilog code for my counter is also similar. But instead, I want to store the value of counter. I tried to write the counter value in slv_reg0 but unfortunately Vivado does not allow it. How can I access this counter value in my SDK? if anyone has solved this problem before, please let me know. 

// Add user logic here
    reg [15:0] counter = 0;

    //simple counter
    always @(posedge S_AXI_ACLK) begin
        if(counter < PWM_COUNTER_MAX-1)
            counter <= counter + 1;
        else
            counter <= 0;
    end

    //comparator statements that drive the PWM signal
    assign PWM0 = slv_reg0 < counter ? 1'b0 : 1'b1;
    assign PWM1 = slv_reg1 < counter ? 1'b0 : 1'b1;
    assign PWM2 = slv_reg2 < counter ? 1'b0 : 1'b1;
    assign PWM3 = slv_reg3 < counter ? 1'b0 : 1'b1;

    // User logic ends

 

[jpeyron]

Hi @vishav,

Please post the code you were trying to implement and the error you got from vivado.

thank you,

Jon