BASYS-3 FPGA cannot generate bitstream

[huletb@my.erau.edu]

I keep getting the following errors when trying to generate a bitstream to upload onto my FPGA, what do they mean? How do I fix them?

 

[DRC NSTD-1] Unspecified I/O Standard: 11 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: A, B, C, D, E, F, G, H, I, J, and K.
[DRC UCIO-1] Unconstrained Logical Port: 11 out of 11 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: A, B, C, D, E, F, G, H, I, J, and K.

[JColvin]

Hi @huletb@my.erau.edu,

The errors indicate that you do not have an xdc file that does not match your project. You will need to add the XDC file to your project and change it as needed. Check out these two tutorials for some more information on how to do this: https://reference.digilentinc.com/learn/software/tutorials/verilog-project-2/start and https://reference.digilentinc.com/learn/software/tutorials/vivado-xdc-file.

Let me know if you have any other questions.

Thanks,
JColvin