Embedded Linux Tutorial

DeAndreHJ · May 16, 2018

Hi, im currently using Vivado 2018.1 on Ubuntu 16.04.3. Im doing the tutorial Embedded Linux Tutorial - Zybo. However, after running synthesis and implementation, im receiving these errors. Im new to the whole digilent, fpga and vivado thing. Sorry if i am unable to convey well enough in my message.

systemgenerate_target all [get_files /home/deandre/zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/system.bd]
[BD 41-1348] Reset pin /axi_dispctrl_0/s_axi_aresetn (associated clock /axi_dispctrl_0/s_axi_aclk) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET1_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /processing_system7_0/FCLK_CLK0.
ipx::edit_ip_in_project -upgrade true -name edit_myLed_v1_0 -directory /home/deandre/zybo_base_system/source/vivado/hw/ip_repo /home/deandre/zybo_base_system/source/vivado/hw/ip_repo/myLed_1.0/component.xml
[BD 41-1273] Error running can_apply_rule TCL procedure: ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors.
    ::bd::board_utils::is_intf_pin Line 3
[BD 5-104] A block design must be open to run this command. Please create/open a block design.
[#UNDEF] Tcl Error in evaluating proc can_apply_rule : ERROR: [Common 17-39] 'get_bd_intf_ports' failed due to earlier errors.
launch_runs impl_1 -to_step write_bitstream
[BD 41-1348] Reset pin /axi_dispctrl_0/s_axi_aresetn (associated clock /axi_dispctrl_0/s_axi_aclk) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET1_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /processing_system7_0/FCLK_CLK0.
[BD 41-1356] Address block </myLed_0/S_AXI/S_AXI_reg> is not mapped into </processing_system7_0/Data>. Please use Address Editor to either map or exclude it.
Synthesis[Common 17-55] 'set_property' expects at least one object. ["/home/deandre/zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/constrs_1/new/base.xdc":1]
ImplementationDesign Initialization[Common 17-55] 'set_property' expects at least one object. ["/home/deandre/zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/constrs_1/new/base.xdc":1]
Place Design[Place 30-58] IO placement is infeasible. Number of unplaced terminals (8) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0 TermDir: In   RangeId: 1 has only 0 sites available on device, but needs 8 sites.
   Term: BTNs_4Bits_tri_i[0]
   Term: BTNs_4Bits_tri_i[1]
   Term: BTNs_4Bits_tri_i[2]
   Term: BTNs_4Bits_tri_i[3]
   Term: SWs_4Bits_tri_i[0]
   Term: SWs_4Bits_tri_i[1]
   Term: SWs_4Bits_tri_i[2]
   Term: and SWs_4Bits_tri_i[3]

[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms |                               Standards                                |                IDelayCtrls               | VREF | VCCO |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 34 |    50 |     6 | LVCMOS33(6)                                                            |                                          |        | +3.30 |    YES |     |
| 35 |    50 |    32 | LVCMOS33(24) TMDS_33(8)                                               |                                          |        | +3.30 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   100 |    38 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

jpeyron · May 16, 2018

Hi @DeAndreHJ,

I would suggest to use a newer project with a petalinux bsp. The newer projects have more functionality improvements. Also Petalinux is mainly a wrapper for yocto. Here is the Petalinux Support for Digilent Boards which has a zybo bps in 2017.2 and 2017.4. The read me has a Quick-Start Guide for getting these projects up and going. In regards to you errors did you manually connect the signal pin reset to the resetn input of the clk_wiz_1 block.

thank you,

Jon

DeAndreHJ · May 17, 2018

hi, i did not manually connect the signal pins resetn input of the clk_wiz_1block. However, i do recall that there wasnt any auto block connection, so, i connected some components following the scehmatics available in the tutorial.

theUltimateSource · May 17, 2018

pin constraints are case sensitive. There's probably some mismatch between your design and constraints.

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