Tim S.

The software driver Makefile for this module was updated to work with Vitis 2020.2 . See: https://github.com/timothystotts/vivado-library/branches branch zybo-z7-20-vivado-2020.2 or arty-a7-100-vivado-2020.2 Regards, Tim S.

The source code and document for this project were updated from using Xilinx Vivado/SDK 2019.1 to Xilinx Vivado/Vitis 2020.2 .

This project was upgraded to Vivado/Vitis 2020.2 .

This project was upgraded to Vivado/Vitis 2020.2 .

This project was release for Vivado/SDK 2019.1, and then upgraded to Vivado/Vitis 2020.2 .

Hi to the community. I have posted on GitHub a FPGA design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS. https://timothystotts.github.io/2020/09/12/hygro-sensor-readings-tester-on-arty-a7.html Regards, Tim S.

Today I authored a brief post to introduce a simple FPGA design that I shared on GitHub. The design inputs a 24-bit color palette value from a keypad; and then that color value is mixed on a discrete RGB LED as well as text on a small display. https://timothystotts.github.io/2020/08/31/colors-palette-tester-on-arty-a7.html Regards, Tim S.

Hi to the community. The GitHub repository now has a section for Lab Verification of the Pmod busses. SPI values are captured with Waveforms as digital logic analyzer to a Pmod TPH2. I authored a Python script that will translate Pmod CLS SPI bus activity and Pmod SF3 SPI bus activity (in separate files) into human-readable statements of the bus transfers. The script: https://github.com/timothystotts/fpga-serial-mem-tester-1/blob/master/Lab-Verification/display_pmod_parse_from_spi_spy.py Example data inputs and outputs: https://github.com/timothystotts/fpga-serial-mem-tester-1/tree/master/Lab-Verification/SF-Tester-Design-VHDL Regards, Tim S.

Hi @JColvin, I'd be glad to have the project(s) shared with the community on Digilent's own Wiki pages. Note that I'll do my best to keep the Git repository copacetic. Thanks! Tim S.

Hello again to the community. I converted my Arty-A7-100 project of a SPI Memory Tester to execute on a Zybo-Z7-20. The design is in Xilinx Vivado and Vitis 2020.1 . You can find a link to the project on my GitHub home page. https://timothystotts.github.io/#fpga-serial-mem-tester-2 Regards, Tim S.

Hi to the community. As with the SPI Accelerometer project, I created a top-level architecture diagram of this project, the Serial Flash Memory Tester. It could help a person decide if there are reusable modules for their own project. Regards, Tim S.

Hi to the community. I would like to mention that I have posted a FPGA design that memory byte tests the Pmod SF3 with 256Mbit N25Q flash chip. You can find a link to this project at http://timothystotts.github.io/. The name of the project is fpga-serial-mem-tester-1 . The project sources contain some features beyond testing the QSPI flash chip. Regards, Tim S.

I authored a minimal Vivado IP design to control a single Pmod SSD with extension cable on a single jack of a FPGA board. The IP is called MuxSSD and allows writing either digit at any time with no need to use a fast GPIO trick in the application C code. This driver is part of my previously mentioned Accelerometer Tester design. The project is hosted at: https://github.com/timothystotts/fpga-serial-acl-tester-1 . Tim S.

Months ago, I wrote a Pmod HYGRO driver in VHDL without block diagram. The Pmod HYGRO's I2C requirements are odd. I'd be glad to mention my findings if you are debugging waveform or message-order issues for reading the HYGRO's measurement registers.

Hi @jpeyron, The base-linux project provides a complex and highly configurable IP Core for the MIPI RX as part of the Board Design. The core is not included under repo/ of the design. It cannot be customized without a license. And it cannot be synthesized without a license. The name of the MIPI RX also differs from the simpler model of the PCam 5 demo. The demo provides MIPI_CSI_2_RX_0 which is an instance of "MIPI CSI-2 Receiver v1.1". The linux base utilizes an absent mipi_csi2_rx_subsystem_0 which is an instance of "MIPI CSI-2 Rx Subsystem v1.0" containing unlicensed core "MIPI CSI-2 Rx Controller v3.0" (Product Guide 232?). Regards, Tim

Specifically, I am using the WebPACK without the SDSoC voucher.

Hi @jpeyron, I am also using Vivado 2017.4 with SDK and support for Zynq-7000 family only. Tim

The exact error message is "Unlicensed Upgrade IP. Check IP license". The needs purchase link indicates minimum version of Vivado as 2017.10 .

Hi @jpeyron, I am unable to upgrade the IP core. Vivado indicates a need to purchase the IP core. Is this IP core not free with WebPACK? Would the SDSoC license voucher provide access to this core? Best regards, Tim

I downloaded Zybo Z7-20 base linux project from git and ran the create_project.tcl script. On the system.bd, there are IP that require a license and are not gratis license. Specifically, the /mipi_csi2_rx_subsystem_0 requires an IP Core license for its sub-component bd_0ac3_rx_0 which.is MIPI CSI-2 Rx Controller. How can I proceed from here for generating a working Zybo Z7-20 linux demo? Thanks. Tim