[Zmod DAC 1411 4096 Sample Limit?]

On 3/21/2024 at 11:26 PM, artvvb said:

Recreating the Vivado project for this demo requires Vivado 2019.1 and the process is documented here: https://digilent.com/reference/programmable-logic/eclypse-z7/git. What version are you using?

Thank you, it's already worked now on baremetal. I think I have some mistakes when checkouting to the correct branch. But, is there a way to import the hardware change so that it can be used on linux project? 

I try to run my linux project, but it's still capped at 4096 samples

[Zmod DAC 1411 4096 Sample Limit?]

On 7/8/2023 at 2:08 AM, artvvb said:

Hi @timmy,

There's a bug in the DMA implementation in Vivado. The "Width of Buffer Length Register" parameter in the DMA configuration should be increased to 16 bits from 14 bits, to increase the amount of data that a single DMA transfer is capable of sending to the circle buffers - this value reflects a maximum number of bytes that can be transferred. Currently, when the length of the transfer is written to the DMA, the top two bits are masked off, and only a quarter of the maximum amount of data can be sent.

Once the hardware is regenerated and the new HDF file has been used to update the hardware platform, no software changes are required to get it working.

Updated sources should be available on Github soon, at least for the baremetal projects.

Thanks,

Arthur

Where can I find the vivado project of the DAC1411_Demo to change the DMA configuration? I'm having the same issue when trying to generate signal with more than 4096 samples by following this tutorial. I've tried to recreate the vivado project of this repo, but in the design file, there's only ZYNQ 7 Processing System IP.

[ADC-DAC Loopback Using ZMOD AWG-1411 and ZMOD ADC-1410]

On 3/20/2024 at 5:36 PM, Cristian.Fatu said:

In order to answer the concern from your initial post, I will tell you some words about the trigger.

ZmodADC, regarded as an data acquisition device, can be configured (through ZMODADC1410 Class functions) to start the acquisition immediately or to start the acquisition only when a specific condition is met. This condition is called trigger condition, and may be defined by setting the trigger level, trigger mode, trigger edge and window position. You can read more details about these on https://digilent.com/reference/zmod/scope/zmodadc1410libraryuserguide.

The function ZMODADC1410::acquireTriggeredPolling starts by setting the trigger (call to ZMODADC1410::setTrigger), prepares the buffer length, starts the acquisition and then waits until a buffer of acquired data is available by polling the buffer full bit. In this moment acquired data is in the buffer, so the only thing left is to perform the DMA transfer of the acquired data.

Below is a explanation of the trigger parameters, taken from the above mentioned user guide.

Thank you very much for the additional explanation 

Here, I want to set the trigger level in two conditions, say that the adc starts polling when the level is above 0.3 V and below -0.3 V. Is there any way to accomplish this?

 

[ADC-DAC Loopback Using ZMOD AWG-1411 and ZMOD ADC-1410]

I've just done trial and error ZMODADC1410::acquireTriggeredPolling function and it's already worked

[ADC-DAC Loopback Using ZMOD AWG-1411 and ZMOD ADC-1410]

Hello, I want to do an ADC-DAC Loopback Using Eclypse Z7 FPGA Board, ZMOD AWG-1411, and ZMOD ADC-1410, programmed using Xilinx SDK. I generate signal and send it from the DAC to the ADC. However, it turns out that the signal captured by the ADC is randomly shifted and sometimes it doesn't captured the signal (only captures noise signal). I want the ADC dan DAC starts simultaneously so that the ADC can captures the signal with short or fixed delay. Is there any idea how to do that?

I follow this DAC and ADC demo linux to create my code below.

I've tried to use std::async but it still doesn't work. I assume using ZMODADC1410::acquireTriggeredPolling should do it, but I still don't understand the trigger concept. Any explanation will be appreciated

Thank you very much

main.cc

[Generates signal from both channels using ZMOD DAC1411]

On 3/14/2024 at 8:30 PM, Cristian.Fatu said:

Hello,
In order to use both (or one) channels you have to:
1. Call allocChannelsBuffer to allocate the buffer, according to the desired size bufSize. It allocates a buffer of 32 bits values (for both channels).
2. Populate the buffer: For each sample (0 to bufSize -1), place in buffer a 32 bits value obtained like this: for each desired channels (two or one) call arrangeChannelData or arrangeSignedChannelData, providing a 16 bits value corresponding to that channel. From these 16 bits, only 14 bits will be used.
3. Call setData function to transfer the buffer to the DAC internal IP buffer
4. Call start function to start the DAC generation process.

For more details see https://digilent.com/reference/zmod/awg/zmoddac1411libraryuserguide

Thank you very much for the explanation. It's really helpful and it's worked :D

[Generates signal from both channels using ZMOD DAC1411]

Hi, i'm currently following this tutorial or demo linux using ZMOD DAC1411 from here. The demo only generates a signal from either channel 1 or channel 2. How to generate signal from both channels? I'm using Eclypse Z7 and Xilinx SDK 2019