JanPeter

Thank you very much for the quick answer! 1. In our understanding, we already use our own constraints file. 2. Further, for the PMOD, we used the same constraints file we previously used for the JTAG: For JTAG (working): ## To use FTDI FT2232 JTAG set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }]; set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }]; set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }]; set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }]; set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }]; For PMOD (not working): ## Debug signals to PMOD set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { trst_n }]; set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { tck }]; set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { tdi }]; set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { tdo }]; set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { tms }]; 3. We tested whether we match the toplevel entity or whether our version is wrong. It was not the problem. So we assume the warnings are not getting rejected. 4. Further, we cannot find any hint in our synthesis or tool messages explaining this ERROR (its attached to this message). Is there another Log except from the one attached here? log.txt

Hello Everyone, I am an Engineer at SYSGO and we work with the Genesys2 board in the TRISTAN research project. For that, we wanted to connect a Lauterbach Debugger vie PMOD to the Genesys2 FPGA. We ran CVA-6 on the FPGA. The problem we encountered was, that we needed to change the PMOD Pin Layout of the FPGA to make it suitable for the Lauterbach Debugger. We used the following Pin layout: ## Debug signals to PMOD set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { trst_n }]; set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { tck }]; set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { tdi }]; set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { tdo }]; set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { tms }]; Also, I tried a different one: set_property IOSTANDARD LVCMOS33 [get_ports trst_n] set_property PACKAGE_PIN E7 [get_ports trst_n] set_property LOC E7 [get_ports trst_n] set_property IOSTANDARD LVCMOS33 [get_ports tck] set_property PACKAGE_PIN J3 [get_ports tck] set_property LOC J3 [get_ports tck] set_property IOSTANDARD LVCMOS33 [get_ports tdi] set_property PACKAGE_PIN K1 [get_ports tdi] set_property LOC K1 [get_ports tdi] set_property IOSTANDARD LVCMOS33 [get_ports tdo] set_property PACKAGE_PIN K2 [get_ports tdo] set_property LOC K2 [get_ports tdo] set_property IOSTANDARD LVCMOS33 [get_ports tms] set_property PACKAGE_PIN E6 [get_ports tms] set_property LOC E6 [get_ports tms] Both layouts giving us the same ERROR: ERROR: [DRC UCIO-1] Unconstrained Logical Port: 5 out of 117 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: trst_n, tms, tdo, tdi, and tck. We cannot figure out why this is happening. We use 3.3V as described in the manual. We would really appreciate support here 🙂 Kind Regards, Jan Reinhard