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GalD101

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Posts posted by GalD101

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    12 minutes ago, reddish said:

    I assume you connected directly, without regard for 50 Ohm termination?

    correct.

     

    I thought that for now I will use the function generator without worrying about impedance and blowing up the FPGA (as my professor told me to, since he wants me to mainly focus on programming the FPGA) so I thought that for now I will just try to learn how to program the FPGA and understand how to control it's clock and how to write to memory. I apologize for my misunderstanding.

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted · Edited by GalD101
    Added function generator and oscilloscope details

    This is the spd we have. I will get info about the function generator as well as the oscilloscope later. 

    https://www.lasercomponents.com/de/?embedded=1&file=fileadmin/user_upload/home/Datasheets/lc-photon-counter/count-nir.pdf&no_cache=1

     

     

    This is the oscilloscope:

    https://www.tequipment.net/Hameg/HM400/Analog-Oscilloscopes/

     

    This is the function generator:

    https://www.thinksrs.com/products/DS345.htm

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    Hi @reddish

    As of now, I'm only limited to using just the function generator. I was able to connect it and make the led blink according to it.

    7 hours ago, reddish said:

    I still want to see a scope image of that

    How can I achieve this? Do you want me to connect the function generator to an oscilloscope?

     

    7 hours ago, reddish said:

    Make an image of what your SPD does on a scope and post it here. Also, post the type/model of your SPD.

    I will try to ask my professor for that since I'm not sure what to do (do I need to connect the spd to an oscilloscope? For now I'm only limited to using the function generator)

    7 hours ago, reddish said:

    Safely (as explained before, with a 50 Ohm terminator) connect the SPD to the FPGA, and program the FPGA to replicate the SPD signal it receives to an output pin (directly, without a clock). Put both signals on a scope. Verify that your FPGA actually detects the SPD signals (this confirms that the signal levels are usable).

    As I said for now I'm limited to using just the function generator instead

    7 hours ago, reddish said:

    Replace the SPD by the function generator programmed to generate a similar but regular signal (similar voltage level, similar pulse length). if that works, you can do most of the remaining development using the function generator rather than with the SPD.

    The function generator is connected to one of the pins in the fpga and it works

     

    7 hours ago, reddish said:

    Learn how to control your FPGA's timing. I proposed earlier that you generate a 30% duty cycle, 10 MHz signal; I still want to see a scope image of that. For this you will need to instantiate an MMCM block inside the FPGA that can synthesize a 100 MHz frequency from the 12 MHz input. If you're at a loss on how to accomplish this, let me know, I can chop this up it in smaller chunks.

    I think I will need some help with that. Are there any good sources for this?

     

    7 hours ago, reddish said:

    I need to hear from you if you are firmly committed to spend this time. Because this is taking a lot of my time as well, which I'm willing to do, but only.if you're serious about getting the project done. You cannot half-ass this; you need to put in the hours.

    Yes, I am committed I just take a data structures course at the same time but no worries, I have until 17.10 to work on this

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    On 8/24/2023 at 5:58 PM, reddish said:

    On the software (HDL) side, this is already a lot more involved. The most challenging part will be to write a bit of VHDL or Verilog to transfer information from the FPGA to the computer. The only feasible way to do that (given your expertise) is via a serial interface. You will write bytes from inside your FPGA to an FPGA output pin that is connected to an FTDI chip on your development board. This FTDI chip will send this data to the PC via USB, where you can receive it using a serial port reading program, for further analysis.

     

    can you help me with this part? where should I start? I will google some information about it

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    On 8/28/2023 at 10:45 AM, reddish said:

    Please explain in your own words what's going on here.

    Isn't this is what's called a "Race Condition"?
    Here, since the two flipflops receive asynchronous input (the input is foreign to their clock),
    a race condition occurs and in the small time difference that is in between the input signal for each ff, the values of flipflop_1 and flipflop_2 are seemingly the same sometimes but in reality, it's just because they sort of like have 2 different inputs that have a "clock" that isn't exactly the same all the time
    by the way, what software/program are you using to draw those images? I saw it before but never bothered to look for it.
     

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    On 8/24/2023 at 5:58 PM, reddish said:

    On the hardware side, this involves making sure that the voltage level output by the SPD is compatible with the voltage input of the FPGA. If you want to do it properly, it would be necessary to make sure that the impedance of the receiving end matches the impedance of the cable coming out of the SPD (usually 50 Ohms), to make sure you don't get reflections of the detection pulses. This is more-or-less optional if the SPD has an output impedance of 50 Ohms, as it will absorb any reflections in that case.

    How can I check this? I have this schematic file and I'm not sure how to read it. Also, how can I figure out the impedance of the cable coming out of the SPD?

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    On 8/25/2023 at 1:09 PM, reddish said:

    why registering externally generated signals that are asynchronous relative to your clock is always a good idea (even if your HDL allows you to not do that).

    ok, so I think that by registering you mean saving as a register (that opposite to a 'wire', it remembers - acts like a memory block) and it is important in order for the timing to be accurate, since the asynchronous signals are not connected to the clock and therefore, if I won't save it in a register (if I won't register the signals), it wouldn't be accurate enough. I'm not sure if that's true, but I think you should also register your output for good practice but it is not as important.

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    On 8/25/2023 at 1:09 PM, reddish said:

    constraints file

    I’m not sure if I really understood what a constrains file is yet, but I think it’s like some sort of a dictionary, I looked here and here and I just used it as a mapping tool between the names of the “variables” in my code to the physical hardware that is on the FPGA. other than that, I’m not sure what else can it be used for. I did see the “create_clock” keyword and I think what you are asking is in reference to this but so far, I just used this file as a dictionary. Is it something that I’m supposed to change or is it supposed to stay like this for the specific device I’m using?

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    On 8/25/2023 at 1:09 PM, reddish said:

    what a "signal assignment" does. Specifically, what is the value of a signal inside a clocked code block right after the assignment statement?

    I’m not sure if I understood you correctly, but if you talk about the assign statement, I think it just makes sure that whenever the value on the right hand side is changing, it changes the state of the value on the left hand side. For example, if I write something like: assign led_b = ~led_g

    then whenever the value of led_g is 0 then led_b will be 1 and when led_g is 1, then led_b will be 0

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted · Edited by GalD101

    On 8/25/2023 at 1:09 PM, reddish said:

    (a) the difference between a combinatoric and a sequential circuit.

    On 8/25/2023 at 1:09 PM, reddish said:

    (c) the difference between combinatorial and sequential circuits.

     

    What’s the difference between a and c?

    From what I understand, in essence, a combinational circuit is a circuit that only depends on its input while a sequential circuit depends on the input as well as its previous output. So you can think of the previous output as some sort of an input as well

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted

    18 hours ago, reddish said:

    To be precise, which of the five experiments described in the paper will you try to replicate?

    For now, we will do the first one with no variations. Later on, we plan to do the rest.

    18 hours ago, reddish said:

    there is also a step 0, which is, to install the Vivado software and learn enough of your favorite HDL (Verilog or VHDL) to make an LED blink on the FPGA board.

    I actually already did exactly this (blinking LED) as well as making the buttons turn the LED on (which is just one line 'assign led = ~btn)

    18 hours ago, reddish said:

    10 nanosecond detection resolution will be enough to establish co-incidence.

    It will be enough.

    p.s. Thanks everyone for the help! I really appreciate it

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted · Edited by GalD101

    @reddish

    Hi, this is really a simplified sketch of the experience and it's not 100% accurate but it should be enough for my part

    we start with two photons that go through a change in their energy level (by going through some sort of medium - a crystal) and then they both reach a corresponding detector.

    Also, excuse my awful handwriting.
    this is the transcript of what's written:
    We want to know when we have a "coincidence", that is, when both detectors are on, within a certain time interval.

     

    Why do we want to check if there are coincidences? because if there is a coincidence, it means the  2 photons were created together as a pair.

     

    Issues that may arise:

    • How would we choose the time interval? (We can choose a sufficiently large time interval such that every detection would count as a coincidence)
    • Following the previous issue, it seems that we may have false positives (coincidence detected but in reality, there was no coincidence) as well as false negatives (coincidence was not detected but in reality, there was a coincidence - "missing a coincidence")
    • HDLs are not programming languages (harder)
    • It's not just an AND gate
    • Clock management and things lick clock domain crossing

    CCU sketch.pdf

    How to use and manage memory with my FPGA?

    in New Users Introduction

    Posted · Edited by GalD101

    Hi @reddish, first of all, thank you for the help. I didn't answer all of your questions since I didn't really understand them. I'm a first-year physics and CS student so I don't have a deep understanding of SPD or FPGA yet. I did talk with my professor and that's what we concluded:

    On 8/20/2023 at 10:07 PM, reddish said:

    - what is the maximum event rate you want to be able to handle?

    I think that we need to measure the maximum event rate according to this link (this is the SPD we have)

    On 8/20/2023 at 10:07 PM, reddish said:

    - are your events reasonably smooth, or do you expect bursts of activity? If yes, can you describe it?

    we have a CW laser so I think the events would be reasonably smooth

    On 8/20/2023 at 10:07 PM, reddish said:

    - how many channels do you need?

    I would like to use 2 and if that would work, I'll try to use 3

    On 8/20/2023 at 10:07 PM, reddish said:

    - what is the time bin resolution you need?

    I'm not sure I think it should approximately be the recovery time of the sensor between each detection.

    On 8/20/2023 at 10:07 PM, reddish said:

    - do you want to make a streaming solution, or have separate capture/transfer stages?

     

    according to what you said, it would probably be a better idea to make a streaming solution since it would be easier.

    On 8/21/2023 at 10:06 PM, reddish said:

    if you're doing this as a lab course for a bachelor or master's degree

    you are correct, I'm doing this as a small project mostly to get some experience doing experiments (I'm in my first year, bachelor's degree).

    On 8/20/2023 at 10:07 PM, reddish said:

    do you understand what "clock domain crossing" means?

    not really but after reading a bit about it, it seems to be the issues that arise when data from one flop transfers data to another with a different clock

    in general, since you seem to be familiar with coincidence counting, do you have any tips on what should I do? I tried reading a lot online and I built very basic projects in Verilog. After reading a bit, I don't think I'll be able to finish this in less than a month but I am very interested in learning more about FPGA and how to program it

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