[How to use and manage memory with my FPGA?]

3 hours ago, reddish said:

 toplevel.sv 383 B · 2 downloads

Why didn't you instantiated the fsm with RESET ? 

[How to use and manage memory with my FPGA?]

Another unrelated question that came across my mind (I'm using the clocking wizard again to generate a 100MHz clock). Why can't I choose a value of M to be 25 and D to be 3 instead of 50 and 6 respectively? Is it just cause or is there a deeper reason as to why, after all 50/6 = 25/3

[How to use and manage memory with my FPGA?]

I also find it a bit confusing that there is no longer a distinction between a reg and a wire with the logic keyword. but it's probably because I'm new to it

[How to use and manage memory with my FPGA?]

1 minute ago, GalD101 said:

because always_ff doesn't allow to?

I think I didn't understand what "event control" is since I found an example with always_ff that has more than one "event" on it's sensitivity list

[How to use and manage memory with my FPGA?]

I looked up always_ff and it seems to be just like the regular always but with restrictions. A bit of an unrelated question: in our case, the good old reg (now logic) will be flipflops only (that is, we will only use ffs for memory (reg)? because I think I once saw that it's also possible to use LUTs instead?) It says that "A always_ff procedure adds a restriction that it can contain one and only one event control and no blocking timing controls" and that "Variables written on the left-hand side of assignments within always_ff... cannot be written by other processes". Why did you choose to use an "always_ff" block in line 44 of my_first_fsm.sv?
Also, in line 44, why won't you add a negedge or posedge of the reset to the sensitivity list like so?

always_ff @ (posedge CLK or negedge RESET) state <= next_state(state, RESET);

I now read a bit about event control and it says on the quote above that always_ff can only use one - so is that the reason you didn't add another event (negedge RESET) to the sensitivity list? because always_ff doesn't allow to? I just want to make sure I understand what event control is.
As for "blocking timing controls" is it that thing you mentioned before (blocking assignments (=) and nonblocking assignments (<=)?) so that is why you used a function that does these operations instead? Also, why did you use a blocking assignment inside the function? I thought we need it to happen simultaneously, or is it because the function is running sequentially but when you do the nonblocking assignment later on line 44 it runs the function and once it's finished you assign it with <= to "state" so it doesn't matter if you did blocking assignments (=) inside the body of the function because you "fix" it when you use non blocking assignment later on line 44?

[How to use and manage memory with my FPGA?]

That seems to be useful too though I haven't read all of it yet

[How to use and manage memory with my FPGA?]

Is it kind of like a superset of Verilog? Similar to how C++ is (kind of) a superset of C

[How to use and manage memory with my FPGA?]

Of course. I'll be looking into it

[How to use and manage memory with my FPGA?]

1 minute ago, reddish said:

does that fit in 1736 cycles?

no....

[How to use and manage memory with my FPGA?]

4 minutes ago, reddish said:

Good! That wasn't so hard was it. Periodicity is a pretty important concept in state machines. Good that we figured out this concept didn't come natural to you. We may need it in the future.

Okay, so your assertion is that the second FSM has a period of 2 * 868 = 1736 clock cycles. I agree that's what it should do.

Now back to the code you posted, with two bugs:
 

  wire [3:0] next_counter = (r_counter + 1) % (868*2 + 1);
  wire       next_fsm_out = (next_counter < 868) ? 1 : 0;

What values does r_counter take on during a full cycle? And how many different values are that? Does that fit in 1736 cycles?


 

it ranges from 0 to 1736 so 1737 different values.
I still don't get the problem with this code:
 

  wire [10:0] next_counter = (r_counter + 1) % (11'd1738);
  wire       next_fsm_out = (next_counter < 10'd867) ? 1'b1 : 1'b0;

 

[How to use and manage memory with my FPGA?]

OK so the first one has a period of 10 since it does 1 1 1 0 0 0 0 0 0 0 and then repeats.
Similarly, the second one has a period of 868*2 since it outputs 1 1 1 1... 868 times and then 0 0 0 0... 868 times and then repeats

[How to use and manage memory with my FPGA?]

what do you mean by period? how often does the output changes?

[How to use and manage memory with my FPGA?]

Just now, reddish said:

Here's the first few states of that state graph.

 

yeah I drew something similar

[How to use and manage memory with my FPGA?]

for 3 clock cycles I get a 1 after that I get a 0 for 7 clock cycles repeat.
for the FSM I'm currently working on, I get a 1 for 868 clock cycles then 0 for 868 clock cycles repeat.

[How to use and manage memory with my FPGA?]

20 hours ago, reddish said:

It should go through that little train of outputs once every 100 ns

.

[How to use and manage memory with my FPGA?]

5 minutes ago, reddish said:

The second bug is a bit more subtle.

What's the period (expressed in clock cycles) of your state machine?
 

100ns? I'm not sure what is it in terms of clock cycles

[How to use and manage memory with my FPGA?]

19 minutes ago, reddish said:

[3:0]

this should probably [10:0] because of the aforementioned so I believe that's one bug

[How to use and manage memory with my FPGA?]

I also see that if I want the register to go up to 868*2 + 1 = 1737 I need to use 11 bits (11011001001)
so that means I need to change the size of the register but you said I have a bug in those lines so I think that's at least another bug

[How to use and manage memory with my FPGA?]

this is what I got with this bit of code:
wire [3:0] next_counter = (r_counter + 1) % (868*2 + 1);
  wire       next_fsm_out = (next_counter < 868) ? 1 : 0;
I don't think that's right
 

[How to use and manage memory with my FPGA?]

Also, I made the 100MHz clock an output as well as the fsm output and it looks like I can see signals of the clock on the pins are physically close to one another

[How to use and manage memory with my FPGA?]

yeah, I had a bug where I wrote a variable in CAPS instead of lowercase lol. this is what I got with this bit of code:
wire [3:0] next_counter = (r_counter + 1) % (10);
wire       next_fsm_out = (next_counter < 3) ? 1 : 0;

[How to use and manage memory with my FPGA?]

Is this what I'm supposed to see? I'm not sure what I need to see here

The signal is very weak

Can you please explain what I'm expected to see after running the modified program?

[How to use and manage memory with my FPGA?]

@reddish what i wrote above (the long post) is it correct? Please correct me if i said something that isn't true
can you please comment on this as well?:

1 hour ago, GalD101 said:

a small question, can't you just make your output (FSM_OUT) a reg and then you wont have to use another auxiliary variable(r_fsm_out)?

EDIT: I think it's not possible to directly change the output but it is possible to use another variable that will be assigned to it like you did

[How to use and manage memory with my FPGA?]

Just now, reddish said:

if you get stuck, ask for help.

I hope I can get scope now. I'll try to ask for one. Thanks

[How to use and manage memory with my FPGA?]

5 minutes ago, reddish said:

Hint: 1/115200.0 seconds is approximately equal to 868 times 10 ns (verify this, then think about the implications given that we have a 100 MHz clock available to us)

so I need to change the code to look like this?:
 

  wire [3:0] next_counter = (r_counter + 1) % (868*2 + 1);
  wire       next_fsm_out = (next_counter < 868) ? 1 : 0;