jbr555

Figured it out, had to change the tcl script and constraint file and now it works as expected

Hello all, I am very new to FPGAs and don't know if what I am trying is doable in a reasonable manner. My objective is to send SPI transactions to flash from JTAG without using Microblaze via the Vivado Tcl consloe. Eventually I want to set password protection on flash sectors after loading a different design, but thought starting with something simpler like reading flash ID would be better. I am using AXI Quad SPI and JTAG to AXI Master IPs and am able to read and modify the AXI registers, but not getting the expected response from flash. Each command I try to send results in the data receive register filling with all Fs. I don't know if the problem is with the design or the Tcl script I am using (attached). Any help would be greatly appreciated. Thanks. My setup is: - Arty S7 50 board - Vivado 2022.2 My block design: The output clock from clock wizard is 100MHz. The external ports are all connected using the board file. JTAG to AXI Master settings: - AXI4Lite, Address Width = 32, Data Width = 31 AXI Quad SPI settings: test_script.tcl