Xband

I have this hardware and software running and giving output on the serial port. When I run the calibration routine it seems to give reasonable data but when I run the S2MM code the output seems to be in hex. My guess is that the cal file isn't referenced properly but its a guess and I can't seem to locate where a file such as this is read in the code, I see the scope_calibration.c file Below are the serial result of the calibration_reader_system and s2mm_cyclic_transfer_test_system. Eventually I want to perform some math on channel acquisitions and spit out a result. I've input a 1kHz +/- 1V sine wave but direct conversion from hex to decimal in Exce (sorry I hate it too) gives nonsense huge numbers column H & I converting B and C. Thanks for any insight. ========= Zmod Port A : Zmod ADC 1410-105 Calibration Coefficients ========= Factory Calibration: December 24, 2021 at 02:55:34 CHAN_1_LG_GAIN: -0.000055 CHAN_1_LG_OFFSET: -0.076329 CHAN_1_HG_GAIN: 0.011868 CHAN_1_HG_OFFSET: -0.002765 CHAN_2_LG_GAIN: -0.001325 CHAN_2_LG_OFFSET: 0.130576 CHAN_2_HG_GAIN: 0.010189 CHAN_2_HG_OFFSET: 0.006026 Ch1LgCoefMultStatic: 0x10CC9 Ch1LgCoefAddStatic: 0x3FE71 Ch1HgCoefMultStatic: 0x11951 Ch1HgCoefAddStatic: 0x3FE97 Ch2LgCoefMultStatic: 0x10C72 Ch2LgCoefAddStatic: 0x002AD Ch2HgCoefMultStatic: 0x118D9 Ch2HgCoefAddStatic: 0x00316 User Calibration: December 24, 2021 at 02:55:34 CHAN_1_LG_GAIN: -0.000055 CHAN_1_LG_OFFSET: -0.076329 CHAN_1_HG_GAIN: 0.011868 CHAN_1_HG_OFFSET: -0.002765 CHAN_2_LG_GAIN: -0.001325 CHAN_2_LG_OFFSET: 0.130576 CHAN_2_HG_GAIN: 0.010189 CHAN_2_HG_OFFSET: 0.006026 Ch1LgCoefMultStatic: 0x10CC9 Ch1LgCoefAddStatic: 0x3FE71 Ch1HgCoefMultStatic: 0x11951 Ch1HgCoefAddStatic: 0x3FE97 Ch2LgCoefMultStatic: 0x10C72 Ch2LgCoefAddStatic: 0x002AD Ch2HgCoefMultStatic: 0x118D9 Ch2HgCoefAddStatic: 0x00316 Done initializing device drivers TestMode: 0 Initialization done ADC initialization done Waiting for trigger... Last beat found: BD base address: 00124168 BD actual length: 0000000C Buffer base address: 00124168 Buffer high address: 00128164 Length of buffer (words): 4096 Index of buffer head: 3 Trigger position: 0 Index of trigger position: 3 Detected trigger condition: 00000002 Transfer done @00124174 FFE70007 3FF9 0001 0 3 @00124178 FFECFFFF 3FFB 3FFF 0 -3 @0012417C FFF0FFEE 3FFC 3FFB 0 -15 @00124180 FFE7FFFF 3FF9 3FFF 0 -3 @00124184 FFDE0003 3FF7 0000 -1 0 @00124188 FFDEFFEA 3FF7 3FFA -1 -18 @0012418C FFD60003 3FF5 0000 -1 0 @00124190 FFDE0003 3FF7 0000 -1 0 @00124194 FFDAFFEA 3FF6 3FFA -1 -18 @00124198 FFEC0003 3FFB 0000 0 0 @0012419C FFECFFFF 3FFB 3FFF 0 -3 @001241A0 FFDA0003 3FF6 0000 -1 0 @001241A4 FFE3FFFB 3FF8 3FFE 0 -6 @001241A8 FFECFFF6 3FFB 3FFD 0 -9 @001241AC 036C0003 00DB 0000 26 0 @001241B0 0BD20035 02F4 000D 92 39 @001241B4 0A9100D5 02A4 0035 82 161 @001241B8 04E60157 0139 0055 38 259 @001241BC 049C0191 0127 0064 36 305 @001241C0 055D01AB 0157 006A 41 323 @001241C4 0611019A 0184 0066 47 311 @001241C8 064601AF 0191 006B 48 326 @001241CC 066901BB 019A 006E 50 335 @001241D0 06B401C0 01AD 0070 52 341 @001241D4 06FF01BB 01BF 006E 54 335 @001241D8 073C01C8 01CF 0072 56 347 @001241DC 078201BB 01E0 006E 58 335 @001241E0 07CD01DD 01F3 0077 60 363 @001241E4 082101E5 0208 0079 63 369 @001241E8 087401DD 021D 0077 66 363 @001241EC 08CC0

@artvvb, I should take this on another thread possibly. I'm reading the AD9648 documents and it is saying that the DCO clocks are used for eternal triggering of the ADC. In a perfect world my application will possibly sent a trigger in through a Pmode channel to initiate the acquisition. I say Pmod because it seems to me to be the existing DIO for the Eclypse board. I've gotten through the above errors and have another query about a function that is causing an error in the Vitus build. "adcZmod()" seems to pop up in multiple places but I cannot determine where it is defined, or where to link to it.

This is the main.c code I"m running. Basically the example with the DAC removed, #include <stdio.h> #include <stdlib.h> #include <unistd.h> #include "platform.h" #include "xil_printf.h" #include "xparameters.h" #include "zmodlib/Zmod/zmod.h" #include "zmodlib/ZmodADC1410/zmodadc1410.h" #define TRANSFER_LEN 0x800 // ZMOD ADC parameters #define ZMOD_ADC_BASE_ADDR XPAR_AXI_ZMODADC1410_0_S00_AXI_BASEADDR #define DMA_ADC_BASE_ADDR XPAR_AXI_DMA_ADC_BASEADDR #define IIC_BASE_ADDR XPAR_PS7_I2C_1_BASEADDR #define FLASH_ADDR_ADC 0x30 #define ZMOD_ADC_IRQ XPAR_FABRIC_AXI_ZMODADC1410_0_LIRQOUT_INTR #define DMA_ADC_IRQ XPAR_FABRIC_AXI_DMA_ADC_S2MM_INTROUT_INTR #define ZMOD_ADC_BASE_ADDR XPAR_AXI_ZMODADC1410_1_S00_AXI_BASEADDR #define DMA_ADC_BASE_ADDR XPAR_AXI_DMA_ADC_BASEADDR #define IIC_BASE_ADDR XPAR_PS7_I2C_1_BASEADDR #define FLASH_ADDR_ADC 0x30 #define ZMOD_ADC_IRQ XPAR_FABRIC_AXI_ZMODADC1410_1_LIRQOUT_INTR //ZMOD DAC parameters Deleted JL /* * Simple ADC test, puts the ADC in the test mode (ramp), * performs an acquisition under specific trigger conditions * and verifies the acquired data to be consistent with these conditions. */ void testZMODADC1410Ramp_Auto() { ZMODADC1410 adcZmod(ZMOD_ADC_BASE_ADDR, DMA_ADC_BASE_ADDR, IIC_BASE_ADDR, FLASH_ADDR_ADC, ZMOD_ADC_IRQ, DMA_ADC_IRQ); if(adcZmod.autoTestRamp(1, 0, 0, 4, TRANSFER_LEN) == ERR_SUCCESS) { xil_printf("Success autotest ADC ramp\r\n"); } else { xil_printf("Error autotest ADC ramp\r\n"); } } /* * Format data contained in the buffer and sends it over UART. * It displays the acquired value (in mV), raw value (as 14 bits hexadecimal value) * and time stamp within the buffer (in time units). * @param padcZmod - pointer to the ZMODADC1410 object * @param acqBuffer - the buffer containing acquired data * @param channel - the channel where samples were acquired * @param gain - the gain for the channel * @param length - the buffer length to be used */ void formatADCDataOverUART(ZMODADC1410 *padcZmod, uint32_t *acqBuffer, uint8_t channel, uint8_t gain, size_t length) { char val_formatted[15]; char time_formatted[15]; uint32_t valBuf; int16_t valCh; float val; xil_printf("New acquisition ------------------------\r\n"); xil_printf("Ch1\tRaw\tTime\t\r\n"); for (size_t i = 0; i < length; i++) { valBuf = acqBuffer[i]; valCh = padcZmod->signedChannelData(channel, valBuf); val = padcZmod->getVoltFromSignedRaw(valCh, gain); padcZmod->formatValue(val_formatted, 1000.0*val, "mV"); if (i < 100) { padcZmod->formatValue(time_formatted, i*10, "ns"); } else { padcZmod->formatValue(time_formatted, (float)(i)/100.0, "us"); } xil_printf("%s\t%X\t%s\r\n", val_formatted, (uint32_t)(valCh&0x3FFF), time_formatted); } } /* * Simple ADC test, acquires data and sends it over UART. * @param channel - the channel where samples will be acquired * @param gain - the gain for the channel * @param length - the buffer length to be used */ void adcDemo(uint8_t channel, uint8_t gain, size_t length) { ZMODADC1410 adcZmod(ZMOD_ADC_BASE_ADDR, DMA_ADC_BASE_ADDR, IIC_BASE_ADDR, FLASH_ADDR_ADC, ZMOD_ADC_IRQ, DMA_ADC_IRQ); uint32_t *acqBuffer; adcZmod.setGain(channel, gain); while(1) { acqBuffer = adcZmod.allocChannelsBuffer(length); adcZmod.acquireImmediatePolling(acqBuffer, length); formatADCDataOverUART(&adcZmod, acqBuffer, channel, gain, length); adcZmod.freeChannelsBuffer(acqBuffer, length); sleep(2); } } /* * Simple DAC test, using simple ramp values populated in the buffer. * @param offset - the voltage offset for the generated ramp * @param amplitude - the amplitude for the generated ramp * @param step - the step between two generated samples * @param channel - the channel where samples will be generated * @param frequencyDivider - the output frequency divider * @param gain - the gain for the channel */ int main() { init_platform(); xil_printf("Hello Eclypse Z7!\n\r"); xil_printf("Testing ADC ZMOD...\n\r"); adcDemo(0, 0, TRANSFER_LEN); cleanup_platform(); return 0; }

I've been through a marathon of directory references trying to get this modified dual ADC project based on the Knitter hello zmod project to build cleanly. Any ideas where this is defined? Stuck now with this undefined ip "adcZmod()" ZMODADC1410 adcZmod(ZMOD_ADC_BASE_ADDR, DMA_ADC_BASE_ADDR, IIC_BASE_ADDR, FLASH_ADDR_ADC, ZMOD_ADC_IRQ, DMA_ADC_IRQ); Thanks,

@artvvb I have the hardware design loaded and a software SOC testing now. Exciting progress! Getting an XAXIDMA_Device_To_DMA transfer length failure now! Progress! Thanks for your continuing support, sorry to have two separate threads on my issues going.

Greetings, this problem is probably obvious to the trained eye, my project consists of 2 Zmod1410 ADC's in the project, trying to generate the 4 channels of data to manipulate in the SOC at some point. Project is based on the Knitter examples in hackster, finally have the constraints working I think and now having clock issues. Three similar errors. The clocks DcoClk_1 and DcoClk_0 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0] TIMING #2 The clocks clk_fpga_0 and clk_fpga_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_1] TIMING #3 The clocks clk_fpga_1 and clk_fpga_0 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_0] Common mode errors accompany these; TIMING #1 The clocks DcoClk_1 and DcoClk_0 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0] Anything else to post to help figure this out. Thanks for any help. report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0] INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-78] ReportTimingParams: -from_pins -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack. WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Date : Tue Sep 12 15:54:22 2023 | Host : JIMT16 running 64-bit major release (build 9200) | Command : report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0] | Design : design_1_wrapper | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.12 2019-11-22 | Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------- Timing Report Slack (MET) : 0.051ns (required time - arrival time) Source: dADC_Data_0[11] (input port clocked by DcoClk_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR/D (rising edge-triggered cell IDDR clocked by DcoClk_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: DcoClk_0 Path Type: Setup (Max at Fast Process Corner) Requirement: 5.000ns (DcoClk_0 fall@5.000ns - DcoClk_1 rise@0.000ns) Data Path Delay: 0.375ns (logic 0.375ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (IBUF=1) Input Delay: 5.440ns Clock Path Skew: 0.904ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.904ns = ( 5.904 - 5.000 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DcoClk_1 rise edge) 0.000 0.000 r input delay 5.440 5.440 J22 0.000 5.440 r dADC_Data_0[11] (IN) net (fo=0) 0.000 5.440 dADC_Data_0[11] J22 IBUF (Prop_ibuf_I_O) 0.375 5.815 r dADC_Data_0_IBUF[11]_inst/O net (fo=1, routed) 0.000 5.815 design_1_i/ZmodADC1410_Controll_1/U0/dADC_Data[11] ILOGIC_X1Y83 IDDR r design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR/D ------------------------------------------------------------------- ------------------- (clock DcoClk_0 fall edge) 5.000 5.000 f M19 0.000 5.000 f DcoClk_0 (IN) net (fo=0) 0.000 5.000 DcoClk_0 M19 IBUF (Prop_ibuf_I_O) 0.151 5.151 f DcoClk_0_IBUF_inst/O net (fo=2, routed) 0.179 5.330 design_1_i/ZmodADC1410_Controll_1/U0/DcoClk BUFIO_X1Y5 BUFIO (Prop_bufio_I_O) 0.483 5.813 f design_1_i/ZmodADC1410_Controll_1/U0/InstDcoBufio/O net (fo=14, routed) 0.091 5.904 design_1_i/ZmodADC1410_Controll_1/U0/DcoBufioClk ILOGIC_X1Y83 IDDR f design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR/C clock pessimism 0.000 5.904 clock uncertainty -0.035 5.868 ILOGIC_X1Y83 IDDR (Setup_iddr_C_D) -0.002 5.866 design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR ------------------------------------------------------------------- required time 5.866 arrival time -5.815 ------------------------------------------------------------------- slack 0.051

I generated a new checkpoint in this menu structure and the issue went away. Not sure if it was the proper thing to do.

I'm wondering if this is another project configuration issue. I've searched this error and worry that the AXI_ZmodADC1410_v1_0.dcp file shouldn't be referenced here. This is my only remaining critical warning after synthesis. Thanks for any insight. Jim

@artvvb, I think that was the problem! Good call. I have a bit of a mess in that sources window for some reason, bringing that to the top now produced a successful synthesized design with only a few errors. I took a day off on the project, thanks for that reply on Thursday! Jim [Synth 8-6895] The reference checkpoint C://GitHub/DualADC_1410_IP/DualADC_1410_IP.srcs/utils_1/imports/synth_1/AXI_ZmodADC1410_v1_0.dcp is not suitable for use with incremental synthesis for this design. Please regenerate the checkpoint for this design with -incremental_synth switch in the same Vivado session that synth_design has been run. Synthesis will continue with the default flow 4 like this, [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port sADC_Sclk_1 can not be placed on PACKAGE_PIN T18 because the PACKAGE_PIN is occupied by port sADC_Sclk_0. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["C://GitHub/DualADC_1410_IP/DualADC_1410_IP.srcs/constrs_1/new/1410ADCmod.xdc":76]

Thanks for finding these typo's, they were from the last change I made, it still should'nt produce a mismatch for every line though should it? Thanks again for all your help on this, hopefully learning something as I go along here. I tried using the earlier ip, the ZmodADC1410_Controller rather than the ZmodScope Controller because there seemed to be few extra ports on the older version. I'm not sure this makes any difference in my current struggles though.

@artvvb I'm not seeing a difference, is it obvious to the trained eye? I've also deleted earlier design wrappers and regenerated everything. Still having the same problem. Pin M20 is duplicated in the constraint file but I wouldn't think that is the main problem. design --Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 --Date : Thu Sep 7 10:40:10 2023 --Host : JIMT16 running 64-bit major release (build 9200) --Command : generate_target design_1_wrapper.bd --Design : design_1_wrapper --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; DcoClk_0 : in STD_LOGIC; DcoClk_1 : in STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; adcClkIn_n_0 : out STD_LOGIC; adcClkIn_n_1 : out STD_LOGIC; adcClkIn_p_0 : out STD_LOGIC; adcClkIn_p_1 : out STD_LOGIC; adcSync_0 : out STD_LOGIC; adcSync_1 : out STD_LOGIC; btn_2bits_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 ); dADC_Data_0 : in STD_LOGIC_VECTOR ( 13 downto 0 ); dADC_Data_1 : in STD_LOGIC_VECTOR ( 13 downto 0 ); rgbled_6bits_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 ); sADC_CS_0 : out STD_LOGIC; sADC_CS_1 : out STD_LOGIC; sADC_SDIO_0 : inout STD_LOGIC; sADC_SDIO_1 : inout STD_LOGIC; sADC_Sclk_0 : out STD_LOGIC; sADC_Sclk_1 : out STD_LOGIC; sCh1CouplingH_0 : out STD_LOGIC; sCh1CouplingH_1 : out STD_LOGIC; sCh1CouplingL_0 : out STD_LOGIC; sCh1CouplingL_1 : out STD_LOGIC; sCh1GainH_0 : out STD_LOGIC; sCh1GainH_1 : out STD_LOGIC; sCh1GainL_0 : out STD_LOGIC; sCh1GainL_1 : out STD_LOGIC; sCh2CouplingH_0 : out STD_LOGIC; sCh2CouplingH_1 : out STD_LOGIC; sCh2CouplingL_0 : out STD_LOGIC; sCh2CouplingL_1 : out STD_LOGIC; sCh2GainH_0 : out STD_LOGIC; sCh2GainH_1 : out STD_LOGIC; sCh2GainL_0 : out STD_LOGIC; sCh2GainL_1 : out STD_LOGIC; sRelayComH_0 : out STD_LOGIC; sRelayComH_1 : out STD_LOGIC; sRelayComL_0 : out STD_LOGIC; sRelayComL_1 : out STD_LOGIC; sys_clock : in STD_LOGIC ); end design_1_wrapper; architecture STRUCTURE of design_1_wrapper is component design_1 is port ( DDR_cas_n : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; btn_2bits_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 ); rgbled_6bits_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 ); sys_clock : in STD_LOGIC; DcoClk_0 : in STD_LOGIC; dADC_Data_0 : in STD_LOGIC_VECTOR ( 13 downto 0 ); DcoClk_1 : in STD_LOGIC; dADC_Data_1 : in STD_LOGIC_VECTOR ( 13 downto 0 ); adcClkIn_p_0 : out STD_LOGIC; adcClkIn_n_0 : out STD_LOGIC; adcSync_0 : out STD_LOGIC; sADC_SDIO_0 : inout STD_LOGIC; sADC_CS_0 : out STD_LOGIC; sADC_Sclk_0 : out STD_LOGIC; sCh1CouplingH_0 : out STD_LOGIC; sCh1CouplingL_0 : out STD_LOGIC; sCh2CouplingH_0 : out STD_LOGIC; sCh2CouplingL_0 : out STD_LOGIC; sCh1GainH_0 : out STD_LOGIC; sCh1GainL_0 : out STD_LOGIC; sCh2GainH_0 : out STD_LOGIC; sCh2GainL_0 : out STD_LOGIC; sRelayComH_0 : out STD_LOGIC; sRelayComL_0 : out STD_LOGIC; adcClkIn_p_1 : out STD_LOGIC; adcClkIn_n_1 : out STD_LOGIC; adcSync_1 : out STD_LOGIC; sADC_SDIO_1 : inout STD_LOGIC; sADC_CS_1 : out STD_LOGIC; sADC_Sclk_1 : out STD_LOGIC; sCh1CouplingH_1 : out STD_LOGIC; sCh1CouplingL_1 : out STD_LOGIC; sCh2CouplingH_1 : out STD_LOGIC; sCh2CouplingL_1 : out STD_LOGIC; sCh1GainH_1 : out STD_LOGIC; sCh1GainL_1 : out STD_LOGIC; sCh2GainH_1 : out STD_LOGIC; sCh2GainL_1 : out STD_LOGIC; sRelayComH_1 : out STD_LOGIC; sRelayComL_1 : out STD_LOGIC ); end component design_1; begin design_1_i: component design_1 port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, DcoClk_0 => DcoClk_0, DcoClk_1 => DcoClk_1, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, adcClkIn_n_0 => adcClkIn_n_0, adcClkIn_n_1 => adcClkIn_n_1, adcClkIn_p_0 => adcClkIn_p_0, adcClkIn_p_1 => adcClkIn_p_1, adcSync_0 => adcSync_0, adcSync_1 => adcSync_1, btn_2bits_tri_i(1 downto 0) => btn_2bits_tri_i(1 downto 0), dADC_Data_0(13 downto 0) => dADC_Data_0(13 downto 0), dADC_Data_1(13 downto 0) => dADC_Data_1(13 downto 0), rgbled_6bits_tri_o(5 downto 0) => rgbled_6bits_tri_o(5 downto 0), sADC_CS_0 => sADC_CS_0, sADC_CS_1 => sADC_CS_1, sADC_SDIO_0 => sADC_SDIO_0, sADC_SDIO_1 => sADC_SDIO_1, sADC_Sclk_0 => sADC_Sclk_0, sADC_Sclk_1 => sADC_Sclk_1, sCh1CouplingH_0 => sCh1CouplingH_0, sCh1CouplingH_1 => sCh1CouplingH_1, sCh1CouplingL_0 => sCh1CouplingL_0, sCh1CouplingL_1 => sCh1CouplingL_1, sCh1GainH_0 => sCh1GainH_0, sCh1GainH_1 => sCh1GainH_1, sCh1GainL_0 => sCh1GainL_0, sCh1GainL_1 => sCh1GainL_1, sCh2CouplingH_0 => sCh2CouplingH_0, sCh2CouplingH_1 => sCh2CouplingH_1, sCh2CouplingL_0 => sCh2CouplingL_0, sCh2CouplingL_1 => sCh2CouplingL_1, sCh2GainH_0 => sCh2GainH_0, sCh2GainH_1 => sCh2GainH_1, sCh2GainL_0 => sCh2GainL_0, sCh2GainL_1 => sCh2GainL_1, sRelayComH_0 => sRelayComH_0, sRelayComH_1 => sRelayComH_1, sRelayComL_0 => sRelayComL_0, sRelayComL_1 => sRelayComL_1, sys_clock => sys_clock ); end STRUCTURE; constraints.xdc # 125MHz Clock from Ethernet PHY set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L12P_T1_MRCC Sch=sysclk create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }]; # Syzygy Port A set_property IOSTANDARD DIFF_SSTL18_I [get_ports -filter { name =~ adcClkIn* }] set_property -dict { PACKAGE_PIN N20 } [get_ports { adcClkIn_n_0 }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n set_property -dict { PACKAGE_PIN N19 } [get_ports { adcClkIn_p_0 }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p set_property SLEW SLOW [get_ports -filter { name =~ adcClkIn* }] set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingL_0 }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0] set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingH_0 }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0] set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS18 } [get_ports { sCh2CouplingL_0 }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1] set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS18 } [get_ports { sCh2CouplingH_0 }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1] set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainL_0 }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3] set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainH_0 }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3] set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainL_0 }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5] set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainH_0 }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5] set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS18 } [get_ports { sRelayComL_0 }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7] set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS18 } [get_ports { sRelayComH_0 }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7] set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS18 } [get_ports { sADC_Sclk_0 }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2] set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS18 } [get_ports { sADC_SDIO_0 }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2] set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS18 } [get_ports { sADC_CS_0 }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26] set_property -dict { PACKAGE_PIN M22 } [get_ports { adcSync_0 }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27] set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ adcSync* }] set_property DRIVE 4 [get_ports -filter { name =~ adcSync* }] set_property SLEW SLOW [get_ports -filter { name =~ adcSync* }] set_property -dict { PACKAGE_PIN M19 } [get_ports { DcoClk_0 }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ DcoClk* }] set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[0] }]; #IO_L16P_T2 Sch=syzygy_a_s[24] set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[1] }]; #IO_L10P_T1 Sch=syzygy_a_s[22] set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[2] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4] set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[3] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6] set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[4] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6] set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[5] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16] set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[6] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18] set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[7] }]; #IO_L10N_T1 Sch=syzygy_a_s[20] set_property -dict { PACKAGE_PIN K20 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[8] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17] set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[9] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4] set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[10] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19] set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[11] }]; #IO_L8N_T1 Sch=syzygy_a_s[21] set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[12] }]; #IO_L8P_T1 Sch=syzygy_a_s[23] set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[13] }]; #IO_L16N_T2 Sch=syzygy_a_s[25] #set_property -dict { PACKAGE_PIN M20 } [get_ports { syzygy_a_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n create_clock -period 10.000 -name DcoClk_0 -waveform {0.000 5.000} [get_ports DcoClk_0] create_generated_clock -name adcClkIn_p_0 -source [get_pins design_1_i/ZmodADC1410_Controll_0/U0/InstADC_ClkODDR/C] -divide_by 1 [get_ports adcClkIn_p_0] set_input_delay -clock [get_clocks DcoClk_0] -clock_fall -min -add_delay 3.240 [get_ports {dADC_Data_0[*]}] set_input_delay -clock [get_clocks DcoClk_0] -clock_fall -max -add_delay 5.440 [get_ports {dADC_Data_0[*]}] set_input_delay -clock [get_clocks DcoClk_0] -min -add_delay 3.240 [get_ports {dADC_Data_0[*]}] set_input_delay -clock [get_clocks DcoClk_0] -max -add_delay 5.440 [get_ports {dADC_Data_0[*]}] # Syzygy Port B set_property IOSTANDARD DIFF_SSTL18_I [get_ports -filter { name =~ adcClkIn* }] set_property -dict { PACKAGE_PIN Y16 } [get_ports { adcClkIn_n_1 }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n set_property -dict { PACKAGE_PIN W16 } [get_ports { adcClkIn_p_1 }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p set_property SLEW SLOW [get_ports -filter { name =~ adcClkIn* }] set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingH_1 }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0] set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingL_1 }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS18 } [get_ports { sCh2CouplingH_1 }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1] set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS18 } [get_ports { s1Ch2CouplingL_1 }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1] set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainL_1 }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3] set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainH_1 }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3] set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainL_1 }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5] set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainH_1 }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5] set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS18 } [get_ports { sRelayComL_1 }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7] set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS18 } [get_ports { sRelayComH_1 }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7] set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS18 } [get_ports { sADC_Sclk_1 }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2] set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS18 } [get_ports { sADC_SDIO_1 }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2] set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS18 } [get_ports { sADC_CS_1 }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26] set_property -dict { PACKAGE_PIN U17 } [get_ports { adcSync_1 }]; #IO_L15N_T2_DQS Sch=syzygy_b_s[27] set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ adcSync* }] set_property DRIVE 4 [get_ports -filter { name =~ adcSync* }] set_property SLEW SLOW [get_ports -filter { name =~ adcSync* }] set_property -dict { PACKAGE_PIN M19 } [get_ports { DcoClk_1 }]; #IO_L13P_T2_MRCC Sch=syzygy_b_p2c_clk_p set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ DcoClk* }] set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[0] }]; #IO_L16P_T2 Sch=syzygy_a_s[24] set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[1] }]; #IO_L10P_T1 Sch=syzygy_a_s[22] set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[2] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4] set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS18 } [get_ports { d1ADC_Data_1[3] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6] set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS18 } [get_ports { d1ADC_Data_1[4] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6] set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[5] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16] set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[6] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18] set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[7] }]; #IO_L10N_T1 Sch=syzygy_a_s[20] set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[8] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17] set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[9] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4] set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[10] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19] set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[11] }]; #IO_L8N_T1 Sch=syzygy_a_s[21] set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[12] }]; #IO_L8P_T1 Sch=syzygy_a_s[23] set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_1[13] }]; #IO_L16N_T2 Sch=syzygy_a_s[25] #set_property -dict { PACKAGE_PIN M20 } [get_ports { syzygy_b_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_b_p2c_clk_n create_clock -period 10.000 -name DcoClk_1 -waveform {0.000 5.000} [get_ports DcoClk_1] create_generated_clock -name adcClkIn_p_1 -source [get_pins design_1_i/ZmodADC1410_Controll_0/U0/InstADC_ClkODDR/C] -divide_by 1 [get_ports adcClkIn_p_1] set_input_delay -clock [get_clocks DcoClk_1] -clock_fall -min -add_delay 3.240 [get_ports {dADC_Data_1[*]}] set_input_delay -clock [get_clocks DcoClk_1] -clock_fall -max -add_delay 5.440 [get_ports {dADC_Data_1[*]}] set_input_delay -clock [get_clocks DcoClk_1] -min -add_delay 3.240 [get_ports {dADC_Data_0[*]}] set_input_delay -clock [get_clocks DcoClk_1] -max -add_delay 5.440 [get_ports {dADC_Data_0[*]}]

@artvvb can I modify the design wrapper along with the constraint file? Since there are 2 zmod 1410 modules the design wrapper has duplicate names for many of the variables.

Thjis is the first time this warning has happened but now it seems none of the names for my constraint file match? I'm not sure actually what they need to match, any insight? This project is using two 1410 ADC's. Now getting that I don't have enough ports. This process is feeling like a slot machine, hopefully will get better. Thanks for any help. This process is very slow, hopefully will get through these errors soon. This project should mimic the zmod scope using 2 1410 ADC zmods. I don't think I've done anything that crazy. Thanks

What am I missing that none of my object names match?

@artvvb, Dug this constraint file out of github. The structure is different but looks like it might be for the Zmod scope setup. Is it ok to drop it in? https://github.com/Digilent/vivado-hierarchies/blob/master/ZmodADC/constrs/ZmodADC.xdc Ran synthesis after getting rid of "Circularbuffer" issues leftover from DAC project, this may have been the cause of some of the earlier errors. Synthesis was successful but seemed to still be looking at my old constraints file, disabled the file and am running again with the above constraints. I don't think it worked. will go back and try to modify the .xdc file again. attached runmelog from C:\Users\Documents\GitHub\DualADC_1410_IP\DualADC_1410_IP.runs\impl_1 runme.log Thanks, JIm

@artvvb I think the problem my have popped up because I started the project first adding the Zynq processor and other parts, running the connection automation along the way, then later I added the "clock wizard" ip. Could have been the root of the issue. I went back and rebuilt the project again and seem to have avoided this problem so far. Thanks again for your help.

I don't understand why the Zmod_DAC is being referenced, it is not in my project anyplace. Built this with 2 ADC 1440's no DAC. Modified the constraints file removing, changing all DAC to ADC reference, maybe a problem there still. Baseline is Knitter "Hello Z-mod" project. I"m just guessing at how to build this constraint file, I'm seeing something about autogenerating the constraint files with a script, "create_hier.tcl"? https://digilent.com/reference/learn/programmable-logic/tutorials/vivado-hierarchical-blocks/start "When create_hier.tcl is run for a Zmod Hierarchical Block, a constraint file is imported which contains template constraints for each external port created by the script. The constraint file is named after the hierarchical block created by the script, followed by the name of the particular Zmod, for example: “ZmodADC_0_ZmodADC.xdc”. The constraint file can be found under the Constraints section of Vivado IP Integrato's Sources pane." [Synth 8-3493] module 'circular_buffer' declared at 'C:/Users/x/Documents/GitHub/DualADC_1410_IP/DualADC_1410_IP.srcs/sources_1/imports/Zmods/AXI_Zmod_DAC1411/src/Circular_Buffer.vhd:51' does not have matching formal port for component port 'saqrunstop' ["C:/Users/x/Documents/GitHub/DualADC_1410_IP/DualADC_1410_IP.srcs/sources_1/imports/Zmods/AXI_Zmod_ADC1410/src/AXI_ZmodADC1410_v1_0.vhd":444] Constriaint file: # 125MHz Clock from Ethernet PHY set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L12P_T1_MRCC Sch=sysclk create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }]; # Syzygy Port A set_property IOSTANDARD DIFF_SSTL18_I [get_ports -filter { name =~ adcClkIn* }] set_property -dict { PACKAGE_PIN N20 } [get_ports { adcClkIn_n_0 }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n set_property -dict { PACKAGE_PIN N19 } [get_ports { adcClkIn_p_0 }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p set_property SLEW SLOW [get_ports -filter { name =~ adcClkIn* }] set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingL_0 }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0] set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS18 } [get_ports { sCh1CouplingH_0 }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0] set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS18 } [get_ports { sCh2CouplingL_0 }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1] set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS18 } [get_ports { sCh2CouplingH_0 }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1] set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainL_0 }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3] set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS18 } [get_ports { sCh2GainH_0 }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3] set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainL_0 }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5] set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS18 } [get_ports { sCh1GainH_0 }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5] set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS18 } [get_ports { sRelayComL_0 }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7] set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS18 } [get_ports { sRelayComH_0 }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7] set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS18 } [get_ports { sADC_Sclk_0 }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2] set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS18 } [get_ports { sADC_SDIO_0 }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2] set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS18 } [get_ports { sADC_CS_0 }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26] set_property -dict { PACKAGE_PIN M22 } [get_ports { adcSync_0 }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27] set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ adcSync* }] set_property DRIVE 4 [get_ports -filter { name =~ adcSync* }] set_property SLEW SLOW [get_ports -filter { name =~ adcSync* }] set_property -dict { PACKAGE_PIN M19 } [get_ports { DcoClk_0 }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p set_property IOSTANDARD LVCMOS18 [get_ports -filter { name =~ DcoClk* }] set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[0] }]; #IO_L16P_T2 Sch=syzygy_a_s[24] set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[1] }]; #IO_L10P_T1 Sch=syzygy_a_s[22] set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[2] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4] set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[3] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6] set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[4] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6] set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[5] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16] set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[6] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18] set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[7] }]; #IO_L10N_T1 Sch=syzygy_a_s[20] set_property -dict { PACKAGE_PIN K20 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[8] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17] set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[9] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4] set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[10] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19] set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[11] }]; #IO_L8N_T1 Sch=syzygy_a_s[21] set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[12] }]; #IO_L8P_T1 Sch=syzygy_a_s[23] set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports { dADC_Data_0[13] }]; #IO_L16N_T2 Sch=syzygy_a_s[25] #set_property -dict { PACKAGE_PIN M20 } [get_ports { syzygy_a_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n create_clock -period 10.000 -name DcoClk_0 -waveform {0.000 5.000} [get_ports DcoClk_0] create_generated_clock -name adcClkIn_p_0 -source [get_pins design_1_i/ZmodADC1410_Controll_0/U0/InstADC_ClkODDR/C] -divide_by 1 [get_ports adcClkIn_p_0] set_input_delay -clock [get_clocks DcoClk_0] -clock_fall -min -add_delay 3.240 [get_ports {dADC_Data_0[*]}] set_input_delay -clock [get_clocks DcoClk_0] -clock_fall -max -add_delay 5.440 [get_ports {dADC_Data_0[*]}] set_input_delay -clock [get_clocks DcoClk_0] -min -add_delay 3.240 [get_ports {dADC_Data_0[*]}] set_input_delay -clock [get_clocks DcoClk_0] -max -add_delay 5.440 [get_ports {dADC_Data_0[*]}] # Syzygy Port B set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[0] }]; #IO_L11P_T1_SRCC Sch=syzygy_b_s[19] set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[1] }]; #IO_L12P_T1_MRCC Sch=syzygy_b_s[18] set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[2] }]; #IO_L7N_T1 Sch=syzygy_b_d_n[6] set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[3] }]; #IO_L10N_T1 Sch=syzygy_b_s[20] set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[4] }]; #IO_L12N_T1_MRCC Sch=syzygy_b_s[16] set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[5] }]; #IO_L11N_T1_SRCC Sch=syzygy_b_s[17] set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[6] }]; #IO_L9N_T1_DQS Sch=syzygy_b_d_n[7] set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[7] }]; #IO_L9P_T1_DQS Sch=syzygy_b_d_p[7] set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[8] }]; #IO_L19N_T3_VREF Sch=syzygy_b_d_n[5] set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[9] }]; #IO_L19P_T3 Sch=syzygy_b_d_p[5] set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[10] }]; #IO_L24N_T3 Sch=syzygy_b_d_n[3] set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[11] }]; #IO_L24P_T3 Sch=syzygy_b_d_p[3] set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[12] }]; #IO_L20N_T3 Sch=syzygy_b_d_n[1] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS18 } [get_ports { sADC_Data_1[13] }]; #IO_L20P_T3 Sch=syzygy_b_d_p[1] set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS18 } [get_ports { sADC_Clkin_1 }]; #IO_L14P_T2_SRCC Sch=syzygy_b_c2p_clk_p set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS18 } [get_ports { sADC_ClkIO_1 }]; #IO_L13P_T2_MRCC Sch=syzygy_b_p2c_clk_p set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS18 } [get_ports { sADC_SDIO_1 }]; #IO_L22P_T3 Sch=syzygy_b_d_p[4] set_property DRIVE 4 [get_ports sADC_SDIO_0] set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS18 } [get_ports { sADC_CS_1 }]; #IO_L22N_T3 Sch=syzygy_b_d_n[4] set_property DRIVE 4 [get_ports SADC_CS_0] set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS18 } [get_ports { sADC_SCLK_1 }]; #IO_L23N_T3 Sch=syzygy_b_d_n[2] set_property DRIVE 4 [get_ports sADC_SCLK_0] set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS18 } [get_ports { sADC_SetFS1_1 }]; #IO_L21P_T3_DQS Sch=syzygy_b_d_p[0] set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { sADC_SetFS2_1 }]; #IO_L21N_T3_DQS Sch=syzygy_b_d_n[0] set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS18 } [get_ports { sADC_Reset_1 }]; #IO_L23P_T3 Sch=syzygy_b_d_p[2] set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS18 } [get_ports { sADC_EnOut_1 }]; #IO_L7P_T1 Sch=syzygy_b_d_p[6] create_generated_clock -name sADC_Clkin_1 -source [get_pins design_1_i/ZmodADC1410_Controll_1/U0/InstADC_ClkinODDR/C] -divide_by 1 [get_ports sADC_Clkin_1] create_generated_clock -name sADC_ClkIO_1 -source [get_pins design_1_i/ZmodADC1410_Controll_1/U0/InstADC_ClkIO_ODDR/C] -divide_by 1 [get_ports sADC_ClkIO_1] set_output_delay -clock [get_clocks sADC_Clkin_1] -clock_fall -min -add_delay -0.100 [get_ports {sADC_Data_1[*]}] set_output_delay -clock [get_clocks sADC_Clkin_1] -clock_fall -max -add_delay 0.250 [get_ports {sADC_Data_1[*]}] set_output_delay -clock [get_clocks sADC_Clkin_1] -min -add_delay -0.100 [get_ports {sADC_Data_0[*]}] set_output_delay -clock [get_clocks sADC_Clkin_1] -max -add_delay 0.150 [get_ports {sADC_Data_1[*]}]

This seems to have some similarity to the question I just posted. My problem was the reset in the "processing_system7_0" for some reason is inverted with respect to the clock wizards signal. My error after validation, [BD 41-238] Port/Pin property POLARITY does not match between /clk_wiz/reset(ACTIVE_HIGH) and /processing_system7_0/FCLK_RESET0_N(ACTIVE_LOW) AMD issue discusses differences in behavior's between using the boot.ini file and a different JTAG setting; https://support.xilinx.com/s/question/0D52E00006lLgyWSAS/polarity-of-reset-issue?language=en_US

My next strange issue, after "validating design" this is the only error, and seems to not have anything to do with Digilent boards or IP? Perhaps the order ip was added was an issue. Is there a simple "invert" function that can be used as a band aide? I can see putting the invert before the Zynq processing FCLK. AMD support suggests an issue with boot.ini or JTAG setting? Found this in AMD support but doesn't really provide a clear solution. I seem to encounter a new issue everytime I rebuild the project I'm trying to make, not near having anything work yet, just keep trying a rebuild, is this a common practice? Thanks for any insight. https://support.xilinx.com/s/question/0D52E00006lLgyWSAS/polarity-of-reset-issue?language=en_US [BD 41-238] Port/Pin property POLARITY does not match between /clk_wiz/reset(ACTIVE_HIGH) and /processing_system7_0/FCLK_RESET0_N(ACTIVE_LOW)

Ok, I think I have it now, added it through "settings" rather than the "+" icon. Don't recall this process previously, Thanks for your help.

@artvvb yes, I've now done it multiple more times, adding this ip directory with the "+" icon in add sources. The demo that I was using was the most recent Dac/adc demo I think, though its difficult to tell. My last try I downloaded the .zip file of the vivado-library in your link, extracted both into my github structure and then into the Vivado/2023.1/data directory and tried then to add the file. Still only see the one library of IP. The ADC/Dac example shows a "User Repository" where these Zmod ip's are, this Repository doesn't show up in a new project. Maybe I'll dig around for adding. "User ip." thanks,

I've had mixed results trying to get project to work. Was finally able to load the ADC/DAC Zmod project in Vivado 2023 but when I try to build my own project I cannot find the Zmod ip to build the block design. I started by trying to modify the ADC/DAC project by deleting the DAC and replacing it with another ADC, since I do not have a DAC, but this seems to overwhelming so wanted to start from scratch in 2023. The approach was to follow the Whittney Knitter Digitizer project and then replace the digitizer with the 1410-105 ADC but the ADC cannot be found in the IP even after trying to add the directories multiple times. In my original ADC/DAC try the 1410-105 ADC is preexising so I can just copy and paste, though I have now confirmed the "ZMOD Scope" is in the IP directory. Its not there when I start a new project though, any thoughts to help me? Getting pretty frustrated with this as everytime I start to make progress a new silly problem appears, probably my novice issue, but still frustrating. I see the available ZmodScope ip in the ADC/DAC example but I cannot add this directory to my new project, why? Thanks,

You’re making a PET coincidence counter? You could use the ADC modules possibility for the input. Even though I’m trying to use the same hardware for another application I haven’t gotten to the point that I can help. The fastest digitizers should work or even the 1410, again I’m not sure on the delay in this board. The FPGA should be adequate, I found a youtube video a guy made on a cheap oscilloscope that uses this exact chip. I’ll follow the conversation.

This example would be nice to reproduce but I cannot find the actual example. I"ve built a couple of other examples with DAC and ADC but I don't have the DAC Zmod and dont care now, just want to acquire and store or process 10us worth of ADC data as a start. Would like to see the actual Vivado project. @artvvb does it exist? Thanks, Jim https://digilent.com/reference/programmable-logic/eclypse-z7/demos/zmod-scope Description This demo uses the Zmod Scope 1410, the initial release of the Zmod ADC IP cores (ZmodADC1410Controller and AXI_Zmod_ADC1410), and the Zmod ADC1410 software library to perform 10 μs captures of an incoming signal. Captured data is written to a file and standard out. Both baremetal and PetaLinux-based projects are provided.

Thanks!