@D@n
Hi Dan. Thanks for writing the comprehensive code! It was very helpful! I tried using your code for the FFT, but I get this error while generating bitstream on my Vivado. Are we supposed to change the code in butterfly.v in order to resolve this?
Thanks for any input!
[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is nolabel_line52/stage_16/FWBFLY.bfly/p3/GENSTAGES[5].genmpy/o_r_reg[25]_0. Please evaluate your design. The cells in the loop are: nolabel_line52/stage_16/FWBFLY.bfly/p3/GENSTAGES[5].genmpy/omem_reg_i_1__0.
