Zhargal

Hello, @zygot! Probably you right about ILA and I overestimate capabilities of using this on higher frequency. I am sending you several Verilog codes, which I was triying to use. First udp_to_rgmii_v1.sv, which works only with certain payload(sorry for lack commenting). Then I decide to rewrite everythting and make some kind of converter from byte to 4 bit bus (rgmii.sv). It was worked well with any random payload. But I've got another problem. When I add the rest of code for reading data from ADC (which is work on 40 MHz) and synchronizing it through fifo_generator (as recommend my friend for synchronizing data with 2 different clock domains), I saw that rgmii output is completely wrong comparing to simulation. For example, it transfers only half of preamble at the beginning (the rest data from each state is also sending only on hald). The rest of code I can't provide. This is private information. Probably you also right about 250 MHz, but I don't know how to design this using only 125 MHz and provide 2 ns time shift at the beginning as it should be. This is probably my last message and you can close this topic, because I need to find another solution to solve this problem. Thanks for all help, which you provide to me, and happy holidays! udp_to_rgmii_v1.sv rgmii.sv

r_clk_in is a differential 200 MHz clock from oscilator in board. For ILA I generate 500 MHz clock to able catch 2 ns gap between TX_CLK and TX[3:0] w_TX_clk is connected to phy_txc_gtxclk. It's 125 MHz as it should be and shifted to 2 ns forward Only transmit, but receiving is working well

Hi @reddish and @zygot! As I've already told you I don't use fixed FCS value, I am using module which is attached in message. In fcs1.png you can see the end of frame for this sequence: ffffffffffff00123456789008004500002eb3fe000080110540c0a8002cc0a8000404000400001a2de8000102030405060708090a0b0c0d0e0f1011 And the result from https://crccalc.com/ is the same so I can consider that this is right result . Now, I want to replace the third and fourth byte (0x0203) to 0xffff with the sequence: ffffffffffff00123456789008004500002eb3fe000080110540c0a8002cc0a8000404000400001a2de80001ffff0405060708090a0b0c0d0e0f1011 The result can be seen in fcs2.png and it's the same as it should be from https://crccalc.com/, but I don't see anything on Wireshark in this case. The result captured from simulation but it's the same on ILA. So for me this is completely zero sense. I just don't know why it's not working. PS I am using Windows as operarting system CRC_gen.v

Hi @reddish and @zygot! The problem with FCS would make sense if I couldn't see absolutely anything or if I put fixed value from example. But FCS recalculates everytime according to all bytes (except preambule at the beginning of course) and I still don't know what is the problem. And no, I don't have any intermediate switch. Looks this is the end for me, because this is complently zero sense for me and no light at the end of the tunnel

Sorry for the late response. Thank you very much for help! At least I found the first mistake. The reason was about inter-frame gap. I've made it longer so now I can at least see example frame. But now I have another problem. I used frame from this example: https://www.fpga4fun.com/10BASE-T2.html, but when I am trying to change payload inside I again don't see anything. All checksums are correct (FCS octet at the end, IP header checksum and UDP checksum). Funny thing that I see that LED is blinking, but Wireshark is silent. So now I am again confused and don't know what to do and where I can find my another mistake

Thank you that you are trying to help. But I don't have time and opportunity for buying another board and don't see any sense for making conversion from GMII-RGMII, since I already see how signal is look like in testbench and ILA.

That is the point that I don't see anything coming back. Well I generate the same sequence from there: https://www.fpga4fun.com/10BASE-T2.html And I still don't see anything coming back in loop mode. Also I manually put ip address and mac address to ARP table. And checksum at the end calculates properly.

Well, I changed values in register to Loop back mode and changed the speed to 100 Mbps. Still don't see anything. The intersting thing that I am capable to read correct PHYID1 and PHYID1 values and catch data from laptop but I still don't know why I can't see anything on laptop side.

Thank you very much for answer! Unfortunately even with 125 MHz and 2 ns data to clock skew, I don't see anything on Wireshark. The last thing I can do is to try values in register to be able using 25 MHz clock. Anyway, why 125 MHz doesn't work is still mistery for me.

Hello, everyone! I want to send some data from ADC using UDP protocol using ethernet on Genesys 2 board, but I don't see anything on Wireshark. Even though, I tried to sent example packet from here: https://www.fpga4fun.com/10BASE-T2.html And even my checksum at the end is calculated properly. I tried 125 MHz at first, then shifted to 25 MHz and still don't know how to handle this. What should I do and how to find my mistake? Even LED on board is blinking and firewall is off in Windows.