Hello, @zygot! Probably you right about ILA and I overestimate capabilities of using this on higher frequency. I am sending you several Verilog codes, which I was triying to use. First udp_to_rgmii_v1.sv, which works only with certain payload(sorry for lack commenting). Then I decide to rewrite everythting and make some kind of converter from byte to 4 bit bus (rgmii.sv). It was worked well with any random payload. But I've got another problem. When I add the rest of code for reading data from ADC (which is work on 40 MHz) and synchronizing it through fifo_generator (as recommend my friend for synchronizing data with 2 different clock domains), I saw that rgmii output is completely wrong comparing to simulation. For example, it transfers only half of preamble at the beginning (the rest data from each state is also sending only on hald). The rest of code I can't provide. This is private information. Probably you also right about 250 MHz, but I don't know how to design this using only 125 MHz and provide 2 ns time shift at the beginning as it should be.
This is probably my last message and you can close this topic, because I need to find another solution to solve this problem. Thanks for all help, which you provide to me, and happy holidays!
udp_to_rgmii_v1.sv
rgmii.sv