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silantyeved

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    Zybo Z7 Petalinux build failure

    in Embedded Linux

    Posted

    I am following this guide: https://digilent.com/reference/programmable-logic/zybo-z7/demos/petalinux

    Petalinux Tools: 2021.1

    BSP Image: Zybo-Z7-10-Petalinux-2021-1.bsp

    After installing petalinux tools in `/opt/pkg/petalinux/` and sourcing `settings.sh`, in the project directory I run:

    `petalinux-create -t project -s Zybo-Z7-10-Petalinux-2021-1.bsp`

    And that executes fine. After I cd into the directory created (`os`), I run `petalinux-build`, which returns errors (attached).

    build.log log.do_configure.1272382

    Arty A7 100 UART echo example [repost]

    in FPGA

    Posted

    That was it, @reddish! Tested with A-G and so far I can see the last 4 bits of each letter being displayed by LEDs as expected. I will test a bit more with the current design and then will do the same but pointing `led_reg` at the first 4 bits instead; or even better, switching between first and last 4 bits using a switch.

    After, I will get to the next portion of you initial suggestion and clean up the RX module interface and then start tying in TX part of the UART.

    Arty A7 100 UART echo example [repost]

    in FPGA

    Posted

    Thanks for your guidance @reddish. My current state of affairs is as follows. I have switched focus to RX side of UART with goal of outputting first (or last?) 4 bits of an ASCII character via Arty's LEDs. While, I am observing some action on the LEDs, it is definitely not consistent with binary representations of characters I am sending to USB file descriptor via UNIX shell. Exact symptoms are as follows:

    When I do:

    echo "A" > /dev/ttyUSB1

    I get the following output on the LEDs (PFA). In fact this output presents itself for any character I try to send. My prime suspect is timing. I am not certain that I have gotten the counter correct, because fiddling with it can lead to different outputs on LEDs, though by no means does it lead to expected output on LEDs. For inspiration I have used Verilog code from https://nandland.com/project-7-uart-part-1-receive-data-from-computer/. Here is the code that I am programming Arty with:  

    `timescale 1ns / 1ps

module top(
  input        clock,
  input        sw1,
  input        sw2,
  output[0:3]  led,
  output[0:3]  led_g,
  input        uart_rx, 
  output       uart_tx 
);

 // UART BAUD
 // (100,000,000 (CLK) / 9600 (BAUD)) =  10417
 parameter CLKS_PER_BIT    = 10417;
 reg [31:0] reg_clks_cnt = 0;

 // RX
 localparam IDLE         = 3'b000;
 localparam RX_START_BIT = 3'b001;
 localparam RX_DATA_BITS = 3'b010;
 localparam RX_STOP_BIT  = 3'b011;
 localparam CLEANUP      = 3'b101;

 reg [3:0] rx_state;
 reg [7:0] rx_byte;
 reg [2:0] rx_byte_idx;
 reg [7:0] led_reg;
 reg [3:0] debug_reg;

 always @(posedge clock)
 begin
     case(rx_state)
     IDLE:
     begin
        reg_clks_cnt <= 0;
        rx_byte_idx  <= 0;
        if (uart_rx == 1'b0) // start bit
        begin
            rx_state       <= RX_START_BIT;
            debug_reg            <= 4'b1111;
        end
        else
        begin
            rx_state       <= IDLE;
        end     
     end
     RX_START_BIT:
     begin
        if (reg_clks_cnt == (CLKS_PER_BIT - 1) / 2)
        begin
            if (uart_rx == 1'b0) // check start bit still low at the middle of BAUD period
            begin
                reg_clks_cnt <= 0;
                rx_state     <= RX_DATA_BITS;                 
            end
            else
            begin
                rx_state     <= IDLE;
            end          
        end
        else
        begin
            // still sampling for the middle of start bit
            reg_clks_cnt <= reg_clks_cnt + 1;
            rx_state     <= RX_START_BIT;
        end     
     end
     RX_DATA_BITS:
     begin
        if (reg_clks_cnt < CLKS_PER_BIT - 1)
        begin
            reg_clks_cnt <= reg_clks_cnt + 1;
            rx_state     <= RX_DATA_BITS;
        end
        else
        begin
            reg_clks_cnt         <= 0;
            rx_byte[rx_byte_idx] <= uart_rx;
            
            if (rx_byte_idx < 7)
            begin
                rx_byte_idx <= rx_byte_idx + 1;
                rx_state     <= RX_DATA_BITS; 
            end
            else
            begin
                rx_byte_idx <= 0;
                rx_state    <= RX_STOP_BIT; 
            end
        end 
     end
     RX_STOP_BIT:
     begin
        if (reg_clks_cnt < CLKS_PER_BIT - 1)
        begin
            reg_clks_cnt <= reg_clks_cnt + 1;
            rx_state     <= RX_STOP_BIT;
        end
        else
        begin
            reg_clks_cnt <= 0;
            rx_state     <= CLEANUP;
        end      
     end
     CLEANUP:
     begin
        rx_state <= IDLE;
     end
     default:
     begin
        rx_state <= IDLE;
     end
     endcase
  end
 
  always @ (posedge clock)
  begin
    if (sw1) begin
        led_reg <= debug_reg;
    end
    else begin
        led_reg <= rx_byte;
    end
  end 
  
  assign led = led_reg;

endmodule

    Any suggestions as to how I can debug this further?

    20221209_173616.jpg

    Arty A7 100 UART echo example [repost]

    in FPGA

    Posted

    @reddish thanks a lot.

    I was able to get a continuous stream of "U"s out in minicom by using 10417 as a count param to switch LEDs (and then UART pin) on and off:

    image.thumb.png.87ebd208367b357cb6ea81fc01321107.png

    I suppose that confirms that:

    1. UART output pin on an FPGA is working as expected

    2. Minicom is set up correctly

    I will appreciate any further guidance you may give me to get the echo working.

    Ed  

    Arty A7 100 UART echo example [repost]

    in FPGA

    Posted

    I want to know if anyone on this forum has ever managed to implement a UART echo application and managed to use tools available in a Unix OS to send and receive serial data (e.g. `minicom`, `echo`). My specific board is Arty a7 100T, but from what I understand the interface is universal (it is in the name) so other board owners input is welcome. 

    Arty A7 100 UART echo example

    in Project Vault

    Posted

    On 11/27/2022 at 9:31 PM, zygot said:

    I typically use Putty to observe UART communications. You have to play with the terminal settings for your setup. Is you FPGA application echoing characters or lines?

    I have set minicom (a unix serial comms utility) to wrap lines on the receiving end. So what I get echo'd back is half the characters that I transmit.

    As to your other suggestion, I will see what I can do with JTAG.

    Arty A7 100 UART echo example

    in Project Vault

    Posted

    Thank you @reddish and @zygot

    I have gotten started with this UART project: https://github.com/projf/projf-explore/tree/main/lib/uart which I can confirm does something on my Arty board. As to whether UART is actually working correctly, I do not know, but here is what I observe:

    I am sending data to the USB descriptor (on which arty board is connected) via:

    echo "AAAA" > /dev/ttyUSB3

    In the other terminal I am running a `minicom` set up with 9600 baud rate with 8N1 configuration and get the following output (when the above echo command is ran):

    AA

    At this point I am not certain why I observe that half the input is being echoed back as my expectation was I would see all of it echoed back. I will continue playing with this project and may be I can figure this out :)

    Arty A7 100 UART echo example

    in Project Vault

    Posted

    I am looking to learn more about peripherals on my board and UART appears to be the best option to start experimenting. Can someone suggest how I could create an echo UART design?

    I would like to communicate to the board as so

    echo "1" > /dev/ttyUSB1

    And would like to read it back, perhaps via

    screen /dev/ttyUSB1 9600

     

    Ed

    Arty A7 100 Ethernet to LEDs Circuit

    in FPGA

    Posted

    Thank you @zygot and your assumption of my skill level is very precise and thanks for managing my expectations.

    For starters, I am not aiming as high as getting two FPGA boards to communicate with each other in an application setting. As mentioned before, my aim is more basic. To expand on an earlier example project I am after: an FPGA board receives a UDP packet with certain content in its body and flashes LEDs with certain light according to that content and/or writes something to UART. Currently, I am still not clear where I would start to build such a project from scratch. My understanding of Ethernet PHYs is not much clearer after a few days of attempts to understand how they work and what's more, I am not sure what's my responsibility to implement and what comes already out of the box. 

    As far as testing / validation is concerned, I would like to set a realistic standard to work towards. I am no stranger to UDP and tools like Wireshark that can help troubleshoot UDP traffic. However, I have never worked with raw Ethernet. On that topic, what would be a minimal set up to validate that FPGA successfully clocked the sent Ethernet packet? How do I even send a raw ethernet packet?

    Arty A7 100 Ethernet to LEDs Circuit

    in FPGA

    Posted

    Thanks @zygot

    I have taken a look at your project and that info went way over my head. I ideally need much more hand holding here. I am surprised there are no resources providing this information. 

    For the time being I am looking into the specs of TI Ehternet PHY that comes with Arty A7 and thinking of the simplest step I can take to get me off the ground. Any further suggestions welcome.

     

    Ed

    Arty A7 100 Ethernet to LEDs Circuit

    in FPGA

    Posted

    Hi,

    I have progressed to wiring FSMs on an Arty board and I would like to delve deeper into ethernet and get a first hand understanding of it. As a base project I am thinking of creating a circuit that would blink board LEDs if a packet with certain content is received.

    I also see that many existing tutorials use ready Ethernet IP cores, which is not what I'd like to do - I want to recreate ethernet from the ground up. How to go about it?

     

    Ed

    Microblaze "Hello World" Tutorials outdated / not working

    in FPGA

    Posted

    I have recently gotten myself an Arty A7 100T board from Digilent. While I was able to do the basic project connecting LEDs to switches, I was not able to get a single tutorial project featuring a Microblaze IP to work. 

    I have followed the following projects to the letter:

    https://digilent.com/reference/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start

    https://projects.digilentinc.com/whitney-knitter/hello-microblaze-on-arty-a7-70d9e1
     

    My set up is Vivado 2022.1 + Vitis on Ubuntu. I realise that both of the above use Arty A7 35T and not 100T, could that be a problem?

    Has anyone ever managed to get Microblaze to work on Arty A7? If so, how did you do it?

    Ed

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