chclau
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Posts posted by chclau
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Hi zygot.
I started to have the same concerns as you when Intel bought Altera. The direction Altera went since it was bought by Intel all but confirmed my fears. And then, to make things worse, AMD bought Xilinx.
I don't know the future either, but the recent announcement from Intel calmed my anxiousness a bit. I commented about this announcement on my blog: https://fpgaer.tech/?p=561. We still need to see what capabilites and prices their "midrange FPGAs" will have, but it is still a ray of hope.
And furthermore, new players are entering the field (of them, I have read quite a few about Effinix, but there are others). So if the worst becomes true and the biggies abandon small and mid range FPGA applications, we can always hope that other players will fill the vacuum.
Cheers.
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Magellan HW monitor for Basys 3 board
Access register bank for reading/writing via JTAG to AXI adapter.
Can also monitor register values via the board seven-segment display (register address is selected through SW0-3)
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A1) You don't need a slave connected for the master to exercise the I2C outputs
A2) Did you check that the address range you defined in the interconnect is the same as it is expected by your .c example code?
A3) You don't need additional HW (Verilog or other) code for this to work. I guess the cause of the problem can be on the address range.
As a proposition for you to debug, try to make a simpler task to check that your system is alive. For example, blink some LEDs from your PS processor using Vitis. Once you have succeeded doing that, go back to more complex problems.
As an additional point, you need to learn how to debug. How to debug the SW using the VITIS, and how to debug HW usign testbenches and ILA (Integrated Logic Analyzer). If you can't see where your problem is, it is difficult to solve it.
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I agree with zygot. If you want to do more than very simple projects, if you want to learn things that will be useful for the industry, make an effort to learn an HDL (Verilog/VHDL). The learning curve is steep, but at least you will have learned something useful for yourself and your career.
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Several VHDL code examples with source code and simulation waveform. Also, at the footer of each example, there is a link to download both the model source and testbench files from GitHub.
The full list is here, and this are the individual code examples:
Binary to seven-segment decoder
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You have to understand the format of the .xdc file that instructs the compiler how to interpret the pins. The error message is above your source file so we cannot see everything but one thing I noticed is that you used a "led" signal. The Basys 3 has several leds so they are numbered. Go through the tutorial again, you should replace on your .xdc files all mentions from "LED[0]" to "led". I don't know the name of t he clock pin you used but I hope you understand the logic of whay you have to do from my answer
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My name is Claudio Avi. I have just received my Basys 3 board.
You can see my FPGA blog here: https://fpgaer.tech
I plan to do several series of projects based on the Basys 3, you can see the first entry for the first (long) project here: https://fpgaer.tech/?p=346
Cheers!
AXI-Lite registers bank, including testbench
in Example projects
Posted
https://fpgaer.tech/?p=447