Riccardo

Ok I understand. At this point I have another question: is there any way I can modify the original code that is working on the FPGA in order to set up a continuous acquisition and manage it with waveforms?

Hello, I recently started to use Waveforms in order to have a simple user interface to communicate with my Digilent Eclypse z7. I'm using it with two adc zmod1410 and a pmod da3. At the moment I'm trying to perform a continuous acquisition of a variable time length signal (in the order of seconds) varying the acquisition frequency during the acquisition. Which is the minimum time delay between two acquisitions of the scope in "repeated" mode? Do you have any suggestion on how can I do with waveforms? I already managed to do it in a bare metal vhdl applications, but when it comes to make it easy to use from a PC I started to meet too many difficulties

Thank you all for your reply, this solved the critical warnings and allowed me to modify the IP

Hello everyone Is there someone who can help me with this problem? I'm going to modify the AXI_ZmodADC1410 IP to let it control two ADC 1410 controller. This is my idea to let only one core of my Eclypse z7 to to control both ADCs (until now I had to connect ADC and core in a one to one fashion) and let the other core to do all the elaborations and transportation to the PC. I started modifying the IP but the problem here is that I can not use the Bus interface of digilent, because I can not find it in the original IP Do you have any suggestion? Thank you very much for your help Have a nice day Riccardo

Thank you zygot for your answer, I had a look around but did not have much time in last days to figure out a solution. Anyway I just realized that the board could have something that can help me without the use of external modules or cables: the USB Micro-AB device. Is this something easy to setup? I see that through the Block diagram in Vivado the USBIND_0 is already mapped into the right FPGA MIOs. If I want to use it, do I only need to use the functions in xusbps.h? Maybe the answer is "you just have to try it and don't bother us with silly questions". What I wanted to know is only if this idea could work or I do not have to take even in consideration. Thank you very much Riccardo

Thank you zygot, I think I will go on with the USB TTL UART cable suggestion: Can this (https://it.farnell.com/ftdi/ttl-232r-3v3/cable-usb-to-ttl-level-serial/dp/1329311?gclid=EAIaIQobChMIqODF3r3v_AIVxY1oCR3wEgQVEAQYASABEgJ-kfD_BwE&mckv=_dc|pcrid||plid||kword||match||slid||product|1329311|pgrid||ptaid|&CMP=KNC-GIT-GEN-SHOPPING-PMAX-NCA-Short-title-test-21-Dec-22&gross_price=true) be ok for the application? I can use two of the pins available form PMOD ports of the Eclypse z7 and use them as TXD and RXD and then connect the ground, is it right? Or is it better a solution with an actual board like this https://ftdichip.com/wp-content/uploads/2020/07/DS_FT4232H_Mini_Module.pdf ?

Thank you zygot for your reply. I am actually using the Vitis serial terminal, which maximum baudrate I can choose is 115200, so maybe even only the 921600 baudrate you are referring can be faster, it the option for the baudrate in the SW code or is there any option to change in the platform.spr file of the hardware project? I will also look at the ethernet application. Do you know any example I can follow? Thank you for your time Riccardo

Hello I have designed a custom acquisition system with the Eclypse z7 modifying the example with the ADC ZMOD1410 https://digilent.com/reference/programmable-logic/eclypse-z7/demos/zmod-scope I managed to acquire a very large amount of data, which I want to transfer to the PC in some way. The method used until now is the uart connection (used as in the example) but it is very poor in speed and in order to transfer the whole acquisition (917448 samples) it takes about 30min! Is there any way in order to speed up the data transfer? I thought about ethernet connection but it seems very difficult to setup for me (I'm a beginner), in addiction I tried to settle up the echo server like in the following forum post but it did not work, as the image reported (Impossible to open a connection with the host n port 7: impossible to connect). Does anyone have a suggestion or an example from where I can tap into?

Hello Udayan, I tried to follow your tutorial on how to setup the ethernet port, but I am not able to ping that address with my laptop. Currently I am using an USB-ethernet adapter because my laptop do not have an ethernet port, but I'm quite sure that it is not representing a problem since I used even in other projects. Is the procedure valid for every PL that uses the Zynq block? I am using Vitis 2021.1 an this is the serial monitor: from this I understand that the ethernet link is settled, but it is not working. Do this happened to you while trying? Thank you in advance Riccardo

Hello Artur, sorry if I bother you I tried to open the project with vivado 2021.1, I migrated it following the procedure of vivado (updated all the IPs) with no modifications on the block diagram or constraints. When it comes time to open a vitis project, when I initially build the empty application (c++) project with the platform generated with the .xsa file coming from the exportation of the Hardware code I receive a makefile error: It seems like vitis can not generate the .elf file. Is there some warnings I have to sort out to be able to build the project?I can leave here the project in a zip file. I tried to do this because I have the same problem on another project I'm borrowing, which uses the same IPs. In the drive folder linked there are both projects: the first one named "hv", the second one (my project) "Adc_acq_system". https://drive.google.com/drive/folders/1OkhMl8JQ3Aqpc8SL3U86NzrDuaPovApL?usp=share_link Thank you for your time Riccardo

Hello Joe, sorry if I open this post again after lot of time. Did you manage to go into the all process without errors? Actually I'm stuck with a makefile error in combination with "ELF file does not exist". Does anyone know how to solve it?

Hi Antonio, I have a problem related to makefile now. The makefile is usually in "Vitis workspace folder"/"name of the project"_system/Debug. Since some time has passed, did you managed to solve the problem? Thank you Riccardo

Hello, I started to go through the customization of that block, in particular into the code for the circular buffer. I have a couple of questions: I don't understant why you initialized the dina and doutb as std_logic_vector(0 downto 0) instead of std_logic_vector(13 downto 0) Why is this process re-initializing all the control variables to '0' or "0" when it starts? I was finding a way to use both port of the Bram in order to read from port B while writing with port A. Is there any constraint you had to follow? I thoughted about creating a process in order to be sure to not read with portB from the same address where port A is writing and leaving the counter enable always active for both ports, do you see any criticity on this? Why are there some signals that are saved many times with R and RR? Is it only a mode to create a clock cycle duration pulse on xsOutAddrCntPulse (in this case)?

Hello artvvb. I'm trying to change the Hardware of the DDR streaming application. Every time I try to open the project this window appears: The problem remains even during the implementation. Is there somethin I did wrong? Currently Im using vivado2021.1. I tried to look for some solutions but it seemed that the only way is to reinstall vivado. In my project I removed the possibility to perform externally the calibration and the relays control, so now the interface for the ADC is the following (with all the control for trigger and son on..), so I'm not even using those ports. Thank you for your time Riccardo

Thank you artvvb! I managed to open it and I have a question: I saw many versions of the ADC ZMod IP, in particular the ZmodADC1410_Control and the ZmodScopeController. I saw that both of them are standalone in applications where no PS is used. I saw even the AXI adapter used in zmod adc-next to interface the ADC controller with the PS: that is the one IP that I hated when I was fighting against that buffer in the acquisition. Is there a way in order to override inside that IP or do I have to re-write that IP without that buffer? Thank you for your time Riccardo

Hello everyone, some of you may know me from this topic I'm currently doing my own design in order to perform a 100s acaquisition with a changing sampling frequency over time with an Eclypse z7 boundled with Zmod ADC1410. In order to test my first HW code I tried with the code used in zmod adc-next (https://github.com/Digilent/Eclypse-Z7-SW/tree/zmod_adc/next), but it did not work. I was wondering if I could open the hardware configuration of that project, but downloading from git (https://github.com/Digilent/Eclypse-Z7-HW/tree/zmod_adc/next) it is impossible to open it in vivado 2019.1. Is here someone who managed to open it? EDIT: furthermore, whenever I try to chenge something/restart the procedure to flash by usb the FPGA, I manage to program the FPGA, but then when it's time to run the code I receive this Even if I designed the HW code on vivado 2021.1 (I'm using vitis 2021.1 for the SW code). The first time I managed to let the code run (but not to work!) I had to restart my pc.

All clear. The fact is that this elapsed time between two acquisitions is too high for my application. The initial idea of using an FPGA acquisition system instead of an oscilloscope is related to the timing: the logaritmic measure I described above comes from the fact that I found limited continuos buffer resource. The real target is to continuosly acquire waveforms, ignoring more samples every decade of time in order to "reduce" the actual sampling frequency (as the image explains), since the more important events are occuring in the first 10ms of the acquisition. In this way even the buffer of the ZMOD IP is someway limiting, that's why I suggested to create a diy version of it. I feel like the real bottleneck is the interface for data transfer from the ZMOD IP and the AXI-DMA. Could this be a method to continuos store data and let the AXI DMA IP save them into the DDR in the meanwhile? To answer: no, it is not necessary to trigger the acquisitions from the second one, it must be triggered only the first one, but this topic opens to the second critical aspect of this setup: the non perfectly equal time between acquisitions would make the measure not precise enought for my application. EDIT: Is the ZMOD IP buffer the FIFO highlighted in the following figure inside "Datapath"? (image took from ZMOD Scope Controller IP user guide) Because on the user guide there is written this: So the next question is (every question that I'm taking is something that I'm studying on, but iI'm happy if you have the answer before me): is the AXI DMA block able to transfer (let's say) instantaneously one single data incoming from the ADC scope controller IP?

Hello Artur, thank you very mch for what you are doing for me. In these days I was testing the board with some codes. Now I'm doing some consequent acquisitions with this code The difference in only_meas it is the comment on the lines that were writing on the serial some debug sentences. What I'm acquiring is descending sawtooth wave with 2Vpp, 10Hz, in order to acquire all the 200us samples in the same period (hoping a delay between two acquisitions<some ms). What i found is in the attached image. This seems to led to a delay that is changing in time and it is less than 50ms (if it was 50ms delay I would have seen a very different type of read waveform) [around 3ms beteen 0u-200u and 200u-400u; while 1.1ms between 800u-1m and 1m-1.2m]. Is it valuable? I think that the best option for me would be to override the internal buffer of the ZMOD ADC IP and to manage directly with a custom PL interface for the ADC all the incoming datas, even if it would be very expensive in term of HW programming. What I need is a delay in time that is stable and around few microseconds. EDIT: I found that the DDR3L memory is not accessible from the PL, but it is hard wired to the PS system, is it? In that case is the DMA IP the only possible access to the DDR3L memory?

Sorry for the long time between your advice and my response. I tried to reset as you said the code is working better: now I can allocate a lot of memory than before, I think there is still some work to do, in particular I want to delete all the time lost in the ZMOD configurations inside "only_meas" before the actual acquisition, so that I can minimize the time between two subsequent acquisitions. My question is: do you think I need to change something inside the HW block diagram to perform the measure described in the previous answers or is it only a matter of SW code?

Nice! This seems to be a good starting point for my objective. I tried and I am able to effectively measure more than before (i reached the 1ms at 100Ms/s). I'm currently stuck due to the impossibility I found in performing two consequent measures (even on the same memory buffer). I need this since 100s at 100Ms/s is too much memory demanding, so we are performing a logaritmic measure, with the first 1ms sampled at the maximum frequency and then with 10 points for each decade, obtained by the mean value of a 200us acquisition. (In addiction the final project will be working with three channels, so with two ZMOD ADC 1410-105). Is there any HW limitation in doing this? My code is the following: And this is the log of the serial port: I'm sorry for these questions, but I'm a beginner in FPGA. Is there any kind of course/resource I can study in order to understand better how to solve certains problem with FPGAs and how to work with them? Thank you very much

UPDATE: Even if I try to force the ADC to store the datas in a new different memory location the result is the same: I'm able to sample only 400us. At this point I'm looking for some errors I'm doing in considering the available memory dimensions larger than what it effectively is. This hypotesis starts from the fact that the ADC buffer is not full

Sorry, forgot a part. Here there is waht is written by the Eclypse on the serial port. 40000 samples are (if I'm not wrong) 40000*32/8= 160000bytes, which is far from the memory of the Eclypse z7 (isn't is?). But I'm not able to find a solution I have not tried yet to sort out the problem related to the first message, I wanted to verify that I'm usin the right functions. Thank you

Hello everyone I'm trying for my project to build up an acquisition system with the Digilent Eclypse z7 board, togheter with the ZMOD ADC1410-105. I'm currently going through the customization of the baremetal example. What I have to do is to sample a 100s voltage transient. In particular I would like to sample the first 1ms with the minimum sampling period (10ns), then I'd like to reduce it for the next decades (let's say 100 samples each decade). At this point I have some questions: Is there any way I can use to allocate a memory buffer longer than the maximum ADC buffer length? Currently I'm using malloc(), since the ZMOD libraries have a sort of protection on memory related functions, but I'm not able to store more than 400us of sampled datas Is it safe to modify the ZMOD libraries? Is there any way I can change the sampling frequency from the software? Currently the idea is to store a 200us buffer and mediate it in order to obtain the point desidered for the decade. (not yet implemented on the code since the first part of the program is not working) Here is the code I'm using and the code I'm refering to: TRANSFER_LEN = 0x2710 main.cpp Memory function with size protection: ZMOD protected function I can not use Sorry for the long question, and sorry for eventual silly mistakes, it's the first time I'm going through these processes and I'm not fully concentrated on this task. Thank you for help. Riccardo

Hello, I have quite the same problem, did you remember how you managed to figure out?

Hello everyone, I'm going to build an acquisition system with the ZMOD ADC 1410 - 105 mounted on the Eclypse z7. My signal is not compliant with the input range specified by the reference manual (I'm going to use the high gain option in order to obtain a higher resolution), so I have to add some conditioning circuits before routing the analog signal into the actual scope. Is the [-1;1] voltage range defined with respect to the Digilent scope ground? I mean, do I have to put in common some ground lines between the acquisition system and the circuit in which there is the voltage I have to sense or not? In order to design the best conditioning circuit, may I have the opportunity to know precisely what is there inside the "amplifier and filter" block? Thank you for your time Riccardo