Hi all,
I have created a block design in vivado,and generate bitstream successfully.Everything seems to be successful,and then i export hardware and create an application project with "Hello world" template,and i did not change anything.
But when i try to program FPGA, i get the following error messages.
" ERROR: [Updatemem 57-153] Failed to update the BRAM INIT strings for ./.../*.elf and ./.../*.mmi "
I'm pretty sure that i have selected the bitfile that was generated earlier.
And here is my block design ,any suggestions?