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Kvass

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    Kvass got a reaction from JColvin in Programmer for custom board   
    As far as I know, as long as you made the JTAG interface on your custom board to match the HS2 pinout, the Adept 2 should recognize the HS2 chip as the "hardware server" and you should be able to see your FPGA and configure it. I use the HS2 programmer to program boards with FPGA parts not from Digilent all the time.
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    Kvass got a reaction from Anthocyanina in Bitstream Generation failed. Vivado 2020.1   
    Take a look at the errors it gives you at the bottom tab of the interface. This should have the reasons why the bitstream generation failed.
     
    It looks like you didn't assign non-default pins in your project. Even if the "default" setting is the one you want, you need to manually assign the pin I/O Standard in the xdc file, or in the pin planner.
     
    ~Kvass
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    Kvass reacted to JColvin in Storing Program in Flash on CMOD A7 in 2022   
    Hi @Kvass,
    I do not have a Cmod A7 with the Macronix memory to directly test this, but this is what I was able to do with the Cmod A7 I have on Vivado/Vitis 2020.2, though I did get a Microblaze application project (a barebones project that spits out "button is pressed" over a serial terminal when you press the onboard Button 1 to light up both LEDs) to load from flash.
    I ended up loosely following two guides (this Instructables guide (which I wrote some more in-depth instructions for on this post here) and Adam Taylors SPI flash guide).
    For the Instructables guide (and in my opinion the easier way to load a Microblaze project into flash since it doesn't use SREC at all) these are the steps that I followed:
     
    These are the steps that I did for Adam Taylor's SREC guide (which also does a similar association of a .elf file in Vivado):
     
    Let me know if you have any questions.
    Thanks,
    JColvin
  4. Like
    Kvass got a reaction from zygot in Genesys ZU 3EG technical issue with JTAG programming   
    Thanks for the responses. I did some digging, and yea, @zygot is right. The JTAG is read after the FMC connector, so is FMC_PRSNTN_M2C is held low, then the FPGA will never get to reading the onboard JTAG port. Somewhat complicates things, but I can work around this information now. 
     

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