[PMODi2s2 Arty z7-10]

Edit 1: I'm using Vivado 2018.2 on Windows 10 Home OS build 19042.1052

I made a custom IP from the files provided in example project available at https://github.com/Digilent/Pmod-I2S2

The IP works at 22.591 MHz procuring a 44.1kHz stereo input of 24-bit depth as AXI-4 stream through its master port.

The same kind of signal can be used for the Transmission as well through its slave port.

So I put a loop back so I'd be sure the signal is received correctly.

I have used a clock converter to match it to the clock I use for the rest of the PL.

It doesn't have internal buffering so cascaded a AXI-4 stream FIFO with it.
Following is my test design: -

Attached is the waveform that I capture using system ILA.

The signal TLAST is asserted every second word hence marking a packet of 2 (3-byte) words.

In my bare-metal code in SDK I use the interrupt mode but the transfer length confuses me.

Please suggest what should be my MAX_PKT_LEN parameter in following command: -

Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, MAX_PKT_LEN , XAXIDMA_DEVICE_TO_DMA);

waveform: -

block diagram: -

Moreover I seem to have an issue with my custom IP core.

Following two warnings appear in the IP editor and it does not appear as a valid interface when connecting board components. So I need to specify pin ports in constraints as well as the diagram.

[IP_Flow 19-570] Bus Interface 'pmod_i2s2': Cannot find bus definition file for "digilentinc.com:interface:pmod:1.0"
[IP_Flow 19-569] Bus Interface 'pmod_i2s2': Cannot find bus abstraction file for "digilentinc.com:interface:pmod_rtl:1.0"

[Arty Z7 DDR/UART access without the PS]

On 7/15/2019 at 11:33 PM, okonomiyonda said:

I'm just getting started with FPGAs, Arty, and Zynq, so I apologise if this is a beginner question or what I'm saying doesn't make total sense.

I'm trying to figure out how to read/write DDR and use the UART from the FPGA side with no involvement from the CPU/PS. I've seen Vivado tutorials where you connect the FPGA over AXI and have the CPU sit in a while loop and printf to the UART. I've seen Vivado tutorials where the CPU sits in a while loop, waits for AXI data or interrupts from the FPGA, reads data from memory, flushes the cache, and sends the data to the FPGA. What I can't seem to find is any examples of the FPGA directly talking to DDR and UART.

What I know so far:

Starting with the image here, it looks like the PL side should be able to talk to DDR and UART over the AMBA interconnect through AXI ports. And indeed, the docs say "cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory" which at least makes me think DDR should be accessible to the FPGA via AXI DMA without PS involvement. I just can't find an example of what I need to do in Vivado to get this hooked up. Separate question: It looks like the PS has a direct connection to DDR that doesn't go over AMBA, so I am wondering what has priority in DDR access, and what the approximate order of magnitude speed difference between CPU uncached direct access and AXI DMA access from the FPGA would be.

Maybe the picture is different for the UART, where I see "the peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space". Again, it looks like both the PL and peripherals are connected to the AMBA interconnect, albeit both as slaves. It also seems that peripheral control registers are only accessible in the processes memory space, but if I can rely on the default reset values, maybe that's not a problem?

So the TL;DR version is Is it possible to read and write DDR from the FPGA without PS involvement? Can I use the UART from the FPGA without PS involvement? Are there any good samples out there I could reference?

@okonomiyonda I hope you are doing Fine.

I want to accomplish the same as u described.
I have a USB to TTL converter and I wish to hookup external interfaces from the block design to the EMIO pins on the board.
Can u point me towards some helpful samples or documents.
 

Reagrds,
 

[FPGA/AXI Audio with ZYNQ and PmodI2S2]

@jungle Can you please share how you got this working
I'm stuck at the interconnection of I2S receiver with Zynq PS.

I used a couple of IPs the FiFo width converter etc. but the problem is with number of bytes.

I2S sends 32 bytes but the DMA controller can handle 1.

Please guide me here I'm a bit stuck.

Regards, 

@artvvbAny help is appreciated.

 

[PMODi2s2 Arty z7-10]

Hi Everyone!

I need help using the following pmodi2s2 module: -
https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/

I want to use it to sample audio data from microphone only. So, I've added the i2s receiver IP into my block diagram (attached) and run block automation.

Following is the documentation of the IP core I used: -
https://www.xilinx.com/support/documentation/ip_documentation/i2s/v1_0/pg308-i2s.pdf

The following is a reference manual for the above mentioned PMOD module: -

https://reference.digilentinc.com/pmod/pmodi2s2/reference-manual

I also created an extra clock in PL fabric named FCLK_CLK1 (11.289MHz requested and got 11.290323 MHz).

I couldn't find a PMOD core for the said module so I guessed I'll "make-external" and "constraint" the pins on to the PMOD header in a .xdc file.

Now, I don't know what to connect where except for the lrclk_out, sclk_out and sdata_0_in which are obvious from their names. Rest of the configuration is auto generated by block automation.

I'm particularly confused regarding the clocking and reset configuration.

Please help me out on this I'll highly appreciate.

[Arty z7-10 MIO pins for UART1]

I have UART1 enabled on MIO 48() 49().

I can't figure out where these pins are on the board.

Please help me out in finding the relevant part from the documentation.

Attached is the screenshot from schematic found at: -

https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty_z7_sch.pdf

Any help is highly appreciated. Its my first post.