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jungle

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  1. @artvvb thanks thats really helpful!
  2. I am new to this so I am just guessing how to out stuff together. I want to use the PmodI2S2 for Stereo Audio Input and Output. I am using a Cora z7 with a ZYNQ. I want to try and make two things: A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data. B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator. The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface. So for part A. I made a new IP with an AXI streaming interface (just one way for line out) and a Pmod output that wraps some of the example code (removing the loop back bit). Then I connected it to DMA. and the DMA to the zynq. Not sure if this makes sense to do.. design_2.pdf But then I am not sure how I get the address in vitis. do I just use the dma address ? I can't work out how it is all translated/mapped. Or.... should I be using a FIFO/ buffer in hardware and writing larger amount of data at a time ?? Is AXI streaming correct should I use something else ? When I create new IP I have the choice: Lite/Full/Stream but when I edit the IP in the packager and add interfaces the AXI interfaces have the following: What is what in here ?? For Part B The example loopback code uses the AXI streaming interface, but what should I use in logic or what would be a normal design for moving audio samples around in fpga ?? Any help
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