Edit 1: I'm using Vivado 2018.2 on Windows 10 Home OS build 19042.1052
I made a custom IP from the files provided in example project available at https://github.com/Digilent/Pmod-I2S2
The IP works at 22.591 MHz procuring a 44.1kHz stereo input of 24-bit depth as AXI-4 stream through its master port.
The same kind of signal can be used for the Transmission as well through its slave port.
So I put a loop back so I'd be sure the signal is received correctly.
I have used a clock converter to match it to the clock I use for the rest of the PL.
It doesn't have internal buffering so cascaded a AXI-4 stream FIFO with it.
Following is my test design: -
Attached is the waveform that I capture using system ILA.
The signal TLAST is asserted every second word hence marking a packet of 2 (3-byte) words.
In my bare-metal code in SDK I use the interrupt mode but the transfer length confuses me.
Please suggest what should be my MAX_PKT_LEN parameter in following command: -
Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, MAX_PKT_LEN , XAXIDMA_DEVICE_TO_DMA);
waveform: -
block diagram: -
Moreover I seem to have an issue with my custom IP core.
Following two warnings appear in the IP editor and it does not appear as a valid interface when connecting board components. So I need to specify pin ports in constraints as well as the diagram.
[IP_Flow 19-570] Bus Interface 'pmod_i2s2': Cannot find bus definition file for "digilentinc.com:interface:pmod:1.0"
[IP_Flow 19-569] Bus Interface 'pmod_i2s2': Cannot find bus abstraction file for "digilentinc.com:interface:pmod_rtl:1.0"