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Yogita

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  1. I am using Nexys-4 DDR Board. I found out what the problem was. The design.txt file did not have enough data points to simulate a sinusoidal signal so, I copied it from the example project into my project and was able to get the desired waveforms. Thanks, Yogita
  2. I want to see the digitalized output with sine wave analog input using xadc wizard. But I am not obtaining sine wave output instead I get a constant output. I have attached the image of the simulation output. The design.txt file is the analog stimulus file stored as example file in xadc. xtest_tb: `timescale 1ns / 1ps module xtest_tb; wire [15 : 0] di_in; wire [6 : 0] daddr_in; wire den_in; wire dwe_in; wire drdy_out; wire [15 : 0] do_out; reg dclk_in; reg reset_in; wire vp_in; wire vn_in; wire [4 : 0] channel_out; wire eoc_out; wire alarm_out; wire eos_out; wire busy_out; initial begin dclk_in=1'b0; forever #5 dclk_in=~dclk_in; end initial begin reset_in=1'b1; #200 reset_in=1'b0; end x_test DUT ( .di_in(16'b0), // input wire [15 : 0] di_in .daddr_in({{2{1'b0}},channel_out}), // input wire [6 : 0] daddr_in .den_in(eoc_out), // input wire den_in .dwe_in(1'b0), .drdy_out(drdy_out), // output wire drdy_out .do_out(do_out), // output wire [15 : 0] do_out .dclk_in(dclk_in), // input wire dclk_in .reset_in(reset_in), // input wire reset_in .vp_in(), // input wire vp_in .vn_in(), // input wire vn_in .channel_out(channel_out), // output wire [4 : 0] channel_out .eoc_out(eoc_out), // output wire eoc_out .alarm_out(alarm_out), // output wire alarm_out .eos_out(eos_out), // output wire eos_out .busy_out(busy_out) // output wire busy_out ); endmodule
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