[Genesys ZU debugging error]

Vitis is very confusing at first. I believe you should create the platform first and then add the application.

What processor are you targeting? Make sure to check the 'generate boot components' box when creating the platform. Double click on the 'platform.spr' file in the explorer and you should see domains for both the fsbl and the pmufw. Are you building the platform before adding the application?

[I2S pmod a/d not working]

I have two I2S pmod boards that appear to have both failed in the same way - there is no output from the a/d converter chip ( ic2 ). I have used both for input and output with an Arty Z7 and have since moved up to a ZCU104 ( Zynq ultrascale+ 7ev MPSoC ) where I, up until recently, was using the output (d/a) section only and thus only connected the 3 (sclk, mclk, lrclk) clocks to the d/a, leaving the a/d unconnected. Wanting to use the a/d, I connected the 3 clocks and the a/d data in the Vivado block diagram and added the 4 pins to the constraints file but was getting zeros only. With an oscilloscope I was able to see an analog signal at the blocking caps (C14 & 15) but no digital signal at pin 1 of IC2, so I'm pretty sure the problem is not with my I2S RTL, block diagram or constraints.

When I was using the Arty Z7 I was always driving  the 3 clocks to both the a/d and d/a even when I wasn't using the a/d. Is it possible that I fried IC2 by using the pmod in slave mode with just the d/a connected?

This is the only thing I can think of that might have caused both to fail in exactly the way. Does anyone have any other ideas? I thought briefly about replacing the chip but there are none available from the usual suppliers.

Thank you, Rich