TOIVI

Thank You @attila !

Hi @TOIVI
Currently the break trigger uses a negative pulse of at least 9 bits long, 1 + uart bits + ?parity, which is on the limit of NUL.
It will be fixed in the next version 3.21.14 to be 10 bits long.
Alternatively configure a pulse trigger of at least 520us

Hi @TOIVI
Thank you.

 

Hi @TOIVI
 

Hí @attila
Yes, I was thinking about the Wankel engine, but I didn't want to complicate the table.
Practically, these are the variants.

Hi @TOIVI
And what about 3 and other stroke numbers ?

Hi @attila
This is a generic solution, but it can be misleading. The attached table summarizes the situation. A 2 Stroke / 4 Stroke switch would be a better option.

Thank You @attila!

Hi @TOIVI
 

I wrote a protocol decoder for the SAE J1850 VPW bus that can be used in WaveForms' Logic Analyzer. I share it.
The decoder works on the DIO 0 channel. It decodes frames and can display bytes (if the DiplayBytes variable is set to true).
I also attach a csv file containing a test sample recorded from a working bus. (This pattern should be imported into the Samples tool for the DIO 0 channel at 346021 Hz.)
Note that the J1850 VPW bus uses a level higher than 5V. Do not connect the input of the logic analyzer  directly to the bus. 

J1850_VPW.txt J1850_VPW_DIO_0.csv J1850_VPW_V2T.txt

Great! Using the native support, the user can connect the oscilloscope tool directly to the vehicle bus,  digitize the signal in mixed mode and decode protocol, eliminating the need for external voltage divider.
(Yes, this unusal bit encoding  is used in J850 VPW. Passive Level Short Pulse = 0, Passive Level Long pulse =1, Active Level Short Pulse =1, Active Level Long Pulse = 0.)
 

Hi @TOIVI

Hi @TOIVI
Thanks for sharing this. I'll add to support it natively.
Edit:
Instead of:
if ((Symbol == 7) || (Symbol == 7)){ //SOF or EOD
you probably wanted:
if ((Symbol == 6) || (Symbol == 7)){ //SOF or EOD

I wrote a protocol decoder for the SAE J1850 VPW bus that can be used in WaveForms' Logic Analyzer. I share it.
The decoder works on the DIO 0 channel. It decodes frames and can display bytes (if the DiplayBytes variable is set to true).
I also attach a csv file containing a test sample recorded from a working bus. (This pattern should be imported into the Samples tool for the DIO 0 channel at 346021 Hz.)
Note that the J1850 VPW bus uses a level higher than 5V. Do not connect the input of the logic analyzer  directly to the bus. 

J1850_VPW.txt J1850_VPW_DIO_0.csv J1850_VPW_V2T.txt