Dram access

[Mahsa]

Hi,

I tried to have a read and write on the DRAM before by AXI MASTER BURST.

which I couldnot! And cannot understand why!

I mean I am quite sure about the functionality of my code reading and writing in burs mode.

but it just work when I use single beat mode I thought it did not write in dram because of coherency issues. But when I try reading in burst it did not work either.

I even thought of address alignment. But as the DRAM addresses starts at 0x00000000 and I am going to read 64bits

I think if I put the length argumant in the function for ex 16, for 2 bursts. It should be work.

any way does not work at all!

 

then I remeber I tried using DMA for reading and writing.

Does anyone have idea, what are the mai differences of these two?

how much data DMA reads each time and is it a pre defined size?

many thanks

[Commanderfranz]

Hi Mahsa,

Before I work on answering your question I was wondering if you could give me some more information,

What board are you using?

Kaitlyn

[Mahsa]

Hi Mahsa,

Before I work on answering your question I was wondering if you could give me some more information,

What board are you using?

Kaitlyn

Hi Kaitlyn,
I am using 7Z045 under Vivado 2015.1

[Commanderfranz]

Hi Mahsa,

Unfortunately since you aren't using any Digilent products I am unable to help you. I would recommend posting in the Xilinx forums.

Kaitlyn