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Do I add the biggest delays up for each bit or is it more involved?

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In an effort to make my serial data processing faster, I attempted to use serial mode 0 with a system clock speed of about 3.686Mhz. Its clock comes from the ALE output of an unprogrammed at89S52 that has a 22.1184Mhz clock attached to it.

Rather than resort to bit-banging, I'm going to try to lower my crystal speed because I was looking at a datasheet for 74HC595 from Texas Instruments and it mentioned about some rise and fall time for 500ns and based on 8051 documentation serial mode 0 makes a clock at 307200Hz (1/12th the 3.6Mhz). I also seen values of 100ns and numbers close to it in both 74HC138 and 74HC595 datasheet as well.

Basically the circuits I show is pretty much a serial to parallel data expander in which the output dataset is selectable by the microcontroller, and also the microcontroller can issue a flush to the registers when its time to display the data.Before this post, I've first read some knowledge about microcontroller. Here is one article I found in a blog called Kynix Semiconductor Electronic Blog

What's the highest speed crystal I should be using for this microcontroller to overcome the propogation delays under the worst-case scenarios (assuming power is 5VDC regulated)?

Do I just add the biggest delays up for each bit or is it more involved?

And when I send the data, I'll be filling all the bits up. Example: for device zero, I'll be filling up all 16-bits and for device 1, I'll be filling up all 24-bits, so the clear functionality of each register is unnecessary as the outputs will eventually be connected to LED's through resistors anyway.


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for the cascaded shift registers, you don't need to add anything.

Once two stages work cleanly [*], you can cascade an infinite number and it'll still work (clock distribution is the bottleneck in reality). That's the beauty of synchronous design.

BTW you will find 74595 variants that are much faster. I've seen one (SMD) double-trigger on a 3 ns reflection on an unterminated cable... That would be the equivalent to 300 MHz... I run mine at 30M.

[*] the theory isn't rocket science, but it does cause the occasional headache.

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There are a lot of considerations when connecting discrete logic to a uC. One is certainly delay. More important is paying attention to min/max logic input/output levels, especially when connecting different logic families together. How the circuit is connected ( PCB, wire-wrap, etc.) is also important.


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