JTAG connection during deep sleep

[cgilbertswatch]

We are using the JTAG USB cable with the ARC core.  Our chip has a deep sleep capability that basically shuts power off to a majority of the part including the JTAG interface.  We are still in the design stage, but are concerned about what the JTAG interface will do when deep sleep is entered.  I assume this is going to disrupt or corrupt our debugging session.  What is likely to happen, and how do we avoid this?  Is there a setting we can use, so that the debugger doesn't think the connection is lost when the part enters deep sleep mode.

[mwingerson]

I had to contact one of our engineers for help on this question.

He said:

"We didn't write the ARC debugger so I don't know how it works. I assume that during a debugging session it sets and reads registers, with the majority of the operations reading a status register. I don't see anything in the 1149.1 JTAG specification describing power saving or sleep modes. The newer 1149.7 spec does appear contain 15-20 pages describing power saving capabilities of 1149.7 compliant tap controllers. I don't know if the ARC core they are using contains an 1149.1 tap or a 1149.7 tap. I think the customers best course of action is to email Synopsys and ask them if the core they licensed supports power saving, and if so, how entering power saving modes impacts any debugging session that they may have open in Metaware (a Synopsys applicaiton)."

I am sorry but I would suggest contacting Synopsys for better help.

Best of luck,

Marshall