I have a Zybo Zynq-7000 Development board, and I'm attempting to create a design that uses the bidirectional HDMI port as an input. I want to take the HDMI input (with a desktop or laptop as the source) and write the video stream to memory, and then access the data in a Linux environment (I am using Xilinux, a graphical, Ubuntu 12.04 LTS-based Linux distribution for the Zynq-7000) to eventually send out the data over the internet. I'm having a bit of difficulty understanding how to correctly implement the design in Vivado (2014.4) which is why I'm here. I'm trying to use as many standard Xilinx or Digilent IP cores as possible to make the design straightforward since I am new to FPGA and Vivado. After wading through tons of documentation, I feel like I have a decent understanding of the general design flow for a video design, but as I said I do not have much experience here so I am looking for someone to hopefully point out my mistakes or point me in the right direction.
1. First and foremost, does my thought process for the design outlined above make any sense? 2. Do I need to use the Video Timing Controller and subsequently the Video Timing Controller IP cores for a design such as this? My assumption here is NO since the input is providing the clock (which in Vivado is being provided to the Video In To AXI4 and VDMA cores), and nothing is being outputted.
3. The DVI2RGB IP Core takes in TMDS as its input. Do I simply create ports labeled TMDS_Clk_p etc and connect to the input of the IP core? How does Vivado know (and subsequently, how does the board know) those ports I created are supposed to be for the HDMI input port?
4. Assuming my design works and I can successfully write the inputted video stream into memory using the VDMA, is the Xilinx Linux VDMA Driver (found here: http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs) my best bet for accessing the data in the VDMA in Linux? Or is Video4Linux2 (V4L2) something that I should be using here? I've read that V4L2 has compatibility with VLC which seems like a convenient way to then stream the video data over the internet.
Additionally, I was able to import an EDK HDMI_RX IP core into Vivado that is used in a Digilent GoPro Video Filtering Project (found here: https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo)Should I be attempting to use this core instead of the DVI2RGB core? I chose the DVI2RGB because it was designed for Vivado rather than EDK, so I assumed it would be easier to use. I would eventually like my design to incorporate audio as well though, which I know DVI doesn't do.
Comments, criticism, advice, help; whatever you've got, it is very welcome here! Anything to steer me in the right direction. Sorry for the long post guys, I've always been a bit verbose I'll attach a screenshot of my Vivado block design to hopefully illustrate some of the things I mentioned about my design. http://i.imgur.com/rdXtuOf.png
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digicloud14
Hi all,
I have a Zybo Zynq-7000 Development board, and I'm attempting to create a design that uses the bidirectional HDMI port as an input. I want to take the HDMI input (with a desktop or laptop as the source) and write the video stream to memory, and then access the data in a Linux environment (I am using Xilinux, a graphical, Ubuntu 12.04 LTS-based Linux distribution for the Zynq-7000) to eventually send out the data over the internet. I'm having a bit of difficulty understanding how to correctly implement the design in Vivado (2014.4) which is why I'm here. I'm trying to use as many standard Xilinx or Digilent IP cores as possible to make the design straightforward since I am new to FPGA and Vivado. After wading through tons of documentation, I feel like I have a decent understanding of the general design flow for a video design, but as I said I do not have much experience here so I am looking for someone to hopefully point out my mistakes or point me in the right direction.
My current design uses a DVI2RGB IP core provided by Digilent (found here: https://github.com/DigilentInc/vivado-library/tree/master/ip/dvi2rgb_v1_4) which is then interfaced with the Xilinx Video In To AXI4-Stream IP Core (documentation found here: http://www.xilinx.com/support/documentation/ip_documentation/v_vid_in_axi4s/v3_0/pg043_v_vid_in_axi4s.pdf), which then goes to the Xilinx AXI Video Direct Memory Access (VDMA) IP core (documentation found here: http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf). Finally, the output of the VDMA is interfaced with an AXI Memory Interconnect to connect it all to the processing system. I do not want to output the video stream that is being written to memory to a display output such as VGA, simply access the video data in Linux and send it out over the internet.
A few questions:
1. First and foremost, does my thought process for the design outlined above make any sense?
2. Do I need to use the Video Timing Controller and subsequently the Video Timing Controller IP cores for a design such as this? My assumption here is NO since the input is providing the clock (which in Vivado is being provided to the Video In To AXI4 and VDMA cores), and nothing is being outputted.
3. The DVI2RGB IP Core takes in TMDS as its input. Do I simply create ports labeled TMDS_Clk_p etc and connect to the input of the IP core? How does Vivado know (and subsequently, how does the board know) those ports I created are supposed to be for the HDMI input port?
4. Assuming my design works and I can successfully write the inputted video stream into memory using the VDMA, is the Xilinx Linux VDMA Driver (found here: http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs) my best bet for accessing the data in the VDMA in Linux? Or is Video4Linux2 (V4L2) something that I should be using here? I've read that V4L2 has compatibility with VLC which seems like a convenient way to then stream the video data over the internet.
Additionally, I was able to import an EDK HDMI_RX IP core into Vivado that is used in a Digilent GoPro Video Filtering Project (found here: https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo)Should I be attempting to use this core instead of the DVI2RGB core? I chose the DVI2RGB because it was designed for Vivado rather than EDK, so I assumed it would be easier to use. I would eventually like my design to incorporate audio as well though, which I know DVI doesn't do.
Comments, criticism, advice, help; whatever you've got, it is very welcome here! Anything to steer me in the right direction. Sorry for the long post guys, I've always been a bit verbose I'll attach a screenshot of my Vivado block design to hopefully illustrate some of the things I mentioned about my design. http://i.imgur.com/rdXtuOf.png
Thank you,
Chris
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