VHDL or Verilog?

[RunningAMuck]

I am looking to familiarize myself with the Basys™2 Spartan-3E FPGA Board and would like to know which text would be most suitable. I am not familiar with VHDL or Verilog. I am interested in the text, "Digital Design" - 2nd edition. Any recommendations to get me started?

 

Thank you!

[hamster]

Both languages are equally powerful when used to implement FPGA designs.

VHDL has an edge when used for design simulation and verification, as it is a richer language.

I find Verilog like Perl - very terse with a lot of stuff happening implicitly. Or maybe C in the pre-ANSI C days.

I find VHDL much more structured, with everything being far more explicit. Because of this it gives you stubby fingers from typing too much.

I you know C, you will find the syntax of Verilog quite familiar, so much that your head will hurt with the confusion.

The choice is also somewhat country dependant, so maybe see what is used locally by looking at a few job ads.

[Alex]

Hi, I agree with Hamster. And actually I will recommend you to use Basys 3 and Vivado Webpack instead of Basys 2. Instead of buying the book, you use the learn.digilentinc.com to learn the digital design. It includes all hands on projects on Verilog. And you read the Read Digital which is freely downloaded at Digilent website to learn the logic theory.

[mearcat]

There's also a blog post about some of the differences between Verilog and VHDL and some of the appropriate occasions for use. https://blog.digilentinc.com/index.php/verilog-vs-vhdl/