Nexys 4 DDR - storing data in memory

[istvank]

Hello,

I'm currently doing a project where I have to take the audio input from the Nexys 4 microphone (for a certain duration like 5 seconds), store it in the memory and then play it through the mono audio output. I'm pretty much done with the serializer and deserializer required for processing the 16-bit audio samples but I got stumped on the memory part. My IDE(vivado)'s design implementation refuses to work after I declare and initialize a memory larger than 9000 addresses. I've done some research and almost everything I've found involves interfacing to DDR(I've studied the provided examples from digilent) but I can't really get to grips with how this interfacing functions. Is there a way to implement this without DDR interfacing or should I try to follow this: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start ?

Thanks in advance!

[D@n]

@istvank,

Yeah, I suppose you could use the SRAM to DDR converter you mentioned above.

You could also use Xilinx's MIG to generate a DDR3 SDRAM controller for you.  The MIG will leave you with either of an AXI interface or a more native interface (which I have no experience with ...)

I've personally taken a third approach, which is to convert the AXI interface to a simpler wishbone interface that I can then work with.  I personally find the wishbone interface much simpler to program for than the AXI interface.  Further, I love the pipelined mode available in the Wishbone B4 specification--primarily because you can use the full memory bandwidth of the bus in that case.  This is the solution I used within my OpenArty project.  I found the details for how to configure the MIG controller within the board file for the Arty--specifically noting that those files are XML files and thus (nearly) human readable--so I could read the configuration necessary back off of them.

As for a controller that you can use to read from a sound port using a wishbone bus, and then write to another sound port, you might find the DMA controller for the ZipCPU sufficient to fit that need.

Incidentally, you can also find a wishbone controlled microphone controller here--it's just not an I2S microphone controller (assuming that was the one you wanted).

Dan

[istvank]

Thank you for your comprehensive answer, I'll study the options and stick with one of them.