I am working with a Digilent Genesys Virtex-5 Development Board and want to implement an LVPECL output clock. The Genesys 1 board has a Virtex-5, which supports LVPECL, but I cannot find the LVPECL output on the Genesys 1?
Looking through Genesys 1 board schematics, I could not find LVPECL_25 outputs as seen in the Virtex-5 FPGA User Guide.
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ee_engineer
Hello there,
I am working with a Digilent Genesys Virtex-5 Development Board and want to implement an LVPECL output clock. The Genesys 1 board has a Virtex-5, which supports LVPECL, but I cannot find the LVPECL output on the Genesys 1?
Looking through Genesys 1 board schematics, I could not find LVPECL_25 outputs as seen in the Virtex-5 FPGA User Guide.
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