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Hello Digilent community,

My name is Lakshmi Morla and I am a student from India ,I have purchased Genesys 2 board for my research project, In regard to that

i wanted to use it with matlab, where i need to prepare it for FPGA in loop. For custom board preparation i require to know regarding IO Standards of the board. Genesys2 board constrain file provides that clock is differential with LVDT IO Standard were as genesys2 board file part0_pins.xml shows that they are TMDS_33 IO Standard, and ethernet pin Mdio has LVCMOS15 (I.E=1.5V) which is not supported with LVDS type clock having 1.8v,TMDS_33 cannot be used as differetial clock( this message generated by vivado ), Please clarify on this regard of Io standards and provide ethernet  Phyaddreres. Reference manual provides contradictory Io pins of Ethernet and other ports which among these files are correct. please help me and I am a novice in this regard.

With Regard,

Morla Lakshmi

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Hello @Lakshmi morla,

The PHY address is in the ref manual: https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual#ethernet_phy

The I/O standard compatibility errors are due to incorrect LOC constraints. Figure 7 in our reference manual shows incorrect locations for Ethernet pins. Please use the XDC file instead that has all the pins and their correct locations. Depending on your application you might need to change the I/O standards for Pmod and FMC signals. Other on-board peripherals should have the correct I/O standard specified and are wired to FPGA banks with compatibility in mind.

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Hello @elodg 

Thank you very much for your support regarding If I stick with XDC file to be correct I have an issue stating that "ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs:  ETH_MDIO (LVCMOS15, requiring VCCO=1.500) and sysclk_p (LVDS, requiring VCCO=1.800)" This is generated by Vivado in a validation test for custom board file in matlab. I am a novice in dealing with FPGA please let me know what does that error mean.I am trying to debug it but notable to do so.

Thank you for your kind support.

with regards,

Lakshmi Morla


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