Lakshmi morla Posted April 28, 2017 Share Posted April 28, 2017 Hello Digilent community, My name is Lakshmi Morla and I am a student from India ,I have purchased Genesys 2 board for my research project, In regard to that i wanted to use it with matlab, where i need to prepare it for FPGA in loop. For custom board preparation i require to know regarding IO Standards of the board. Genesys2 board constrain file provides that clock is differential with LVDT IO Standard were as genesys2 board file part0_pins.xml shows that they are TMDS_33 IO Standard, and ethernet pin Mdio has LVCMOS15 (I.E=1.5V) which is not supported with LVDS type clock having 1.8v,TMDS_33 cannot be used as differetial clock( this message generated by vivado ), Please clarify on this regard of Io standards and provide ethernet Phyaddreres. Reference manual provides contradictory Io pins of Ethernet and other ports which among these files are correct. please help me and I am a novice in this regard. With Regard, Morla Lakshmi Link to comment Share on other sites More sharing options...
This topic is now archived and is closed to further replies.