External variable clock setting for Basys 2

[Alex]

How can I set up a variable clock signal on Basys 2? 

[hamster]

Hi Hamster, thanks for the answer. I should be clearer on my question. Actually, what I want to do is just ramp up the clock and then make a clock divider to generate a list of usable clock. I think your suggested way works perfectly except I third one. Will there be any gated clock warning? 

 

It depends how you do it...

 

If you do it like this you will be safe:

 

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL; entity gated_clock_test is    Port ( clk : in  STD_LOGIC;           control_sw : in  STD_LOGIC;           leds : out  STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is   signal counter      : unsigned(7 downto  0); begin   leds <= std_logic_vector(counter);   p: process(clk)   begin      if rising_edge(clk) and control_sw = '1' then         counter <= counter+1;      end if;   end process; end Behavioral;

 

If you do it like this you will get a gated clock warning:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL; entity gated_clock_test is    Port ( clk : in  STD_LOGIC;           control_sw : in  STD_LOGIC;           leds : out  STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is   signal counter      : unsigned(7 downto  0);   signal gated_clock : std_logic;begin   leds <= std_logic_vector(counter);   gated_clock  <= clk and control_sw;   p: process(gated_clock)   begin      if rising_edge(gated_clock) then         counter <= counter+1;      end if;   end process; end Behavioral;

You can however do exactly the same like this, using a clock buffer with a 'clock enable' signal:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;Library UNISIM;use UNISIM.vcomponents.all; entity gated_clock_test is    Port ( clk : in  STD_LOGIC;           control_sw : in  STD_LOGIC;           leds : out  STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is   signal counter      : unsigned(7 downto  0);   signal gated_clock : std_logic;begin   leds <= std_logic_vector(counter); BUFGCE_inst : BUFGCE port map (      O  => gated_clock, -- Clock buffer ouptput      CE => control_sw,  -- Clock enable input      I  => clk          -- Clock buffer input   );   p: process(gated_clock)   begin      if rising_edge(gated_clock) then         counter <= counter+1;      end if;   end process; end Behavioral;

But if you really just need relatively slow logic then a clock divider is the way to go - everything stays in the same clock domain, so you don't get timing issues when slow logic talks to fast logic:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;Library UNISIM;use UNISIM.vcomponents.all; entity gated_clock_test is    Port ( clk : in  STD_LOGIC;           leds : out  STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is   signal counter        : unsigned(7 downto  0);   signal two_in_nine    : std_logic_vector(8 downto 0) := "100010000";   signal control_2_in_9 : std_logic := '0';begin   leds <= std_logic_vector(counter);    -----------------------------------------   -- Process to manage the the clock enable   -----------------------------------------divide_clock: process(clk)   begin      if rising_edge(clk) then         control_2_in_9 <= two_in_nine(0);         two_in_nine <= two_in_nine(7 downto 0) & two_in_nine(8);      end if;   end process;    --------------------------------   -- Process to do the actual work   --------------------------------p: process(clk)   begin      if rising_edge(clk) and control_2_in_9 = '1' then         counter <= counter+1;      end if;   end process; end Behavioral;

[hamster]

Plenty of ways...but your question is a bit vague.

 

Here are a few options.

 

- You can supply an logic-level clock to one the PMOD pins, and use that as the clock signal in your design.

- You can use the on-board clock and make a fractional clock generator (which will have pretty bad jitter, as the resolution is limited by the clock rate of the fractional clock generator)

- You can use a "clock enable" signal that is not asserted on every clock cycle, to slow your design down

- You can use a Digital Clock Manager (DCM) to generate quite a few different clocks, and then switch between them (perfect if all the clock rates are known in advance)

- You can use a DCM_CLKGEN, where you can reprogram the DCM's multiply or divide frequency on the fly (e.g. to switch a large amount of logic between a few fixed clocks)

....

Or you can do a mix of the above techniques!

 

It really depends on WHY you want a variable clock, and HOW you intend to use it... what are you trying to do?

[Alex]

Hi Hamster, thanks for the answer. I should be clearer on my question. Actually, what I want to do is just ramp up the clock and then make a clock divider to generate a list of usable clock. I think your suggested way works perfectly except I third one. Will there be any gated clock warning? 

[Alex]

Hi Hamster, thanks for the information. It is very helpful.