Hi, I'm just beginning with FPGA's, I bought a Basys 3 this past tuesday.
I'm trying to increment a 4-bit value with the on-board Up-button and decrease it with the Down-button. What is a straight forward way of doing this?? I've tried to get this to work for the last two days. The buttons are debounced, so that's not an issue.
I've tried keeping the value in a signal vector and depending on which button is pressed, add a one or add a two's complement -1. The adding is done with a 4 bit adder I built, which works.
I'm sort of new to VHDL and digital design so any useful tips or hints or general advice are very much appreciated.
Instead of getting 1, 2, 3, 4, 5, 6 etc when pressing the Up button, I get a very weird pattern.. See attached photo (the arrows were meant to show that the pattern repeated itself after a number of presses).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity btn_map is
Port ( btnD, btnU : in STD_LOGIC; --btnU/D stands for up/down
key : out STD_LOGIC_VECTOR (3 downto 0));
end btn_map;
architecture Behavioral of btn_map is
component trig_4b_Adder is
Port ( clk : in STD_LOGIC; --I modified the adder with some D-flops to not create a combinatorial loop (hence the clk)
c, y : in STD_LOGIC_VECTOR (3 downto 0); --c/y are the two 4-bit inputs to the adder
s : out STD_LOGIC_VECTOR (3 downto 0)); --s = result
end component;
signal val, add_sub, new_key : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal trigger : STD_LOGIC := '0'; -- clock for the adder, "keypressed"
begin
Adder: trig_4b_Adder port map(clk => trigger, c => val, y => add_sub, s => new_key); -- add_sub is either the +1, -1 or 0
process(btnD, btnU)
variable minus : STD_LOGIC_VECTOR (3 downto 0) := "1111";
variable plus : STD_LOGIC_VECTOR (3 downto 0) := "0001";
variable zero : STD_LOGIC_VECTOR (3 downto 0) := "0000";
begin
if btnD = '1' then
add_sub <= minus;
elsif btnU = '1' then
add_sub <= plus;
else
add_sub <= zero; -- (sub zero lol)
end if;
end process;
trigger <= btnU or btnD; -- start the adder
val <= new_key; -- I want to save the result from the adder till next clock cycle -- these two lines of code feel bad for some reason,
key <= new_key; -- key is the output from this module -- like my design is inherently flawed somehow..
end Behavioral;
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Hi, I'm just beginning with FPGA's, I bought a Basys 3 this past tuesday.
I'm trying to increment a 4-bit value with the on-board Up-button and decrease it with the Down-button. What is a straight forward way of doing this?? I've tried to get this to work for the last two days. The buttons are debounced, so that's not an issue.
I've tried keeping the value in a signal vector and depending on which button is pressed, add a one or add a two's complement -1. The adding is done with a 4 bit adder I built, which works.
I'm sort of new to VHDL and digital design so any useful tips or hints or general advice are very much appreciated.
Instead of getting 1, 2, 3, 4, 5, 6 etc when pressing the Up button, I get a very weird pattern.. See attached photo (the arrows were meant to show that the pattern repeated itself after a number of presses).
library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity btn_map is Port ( btnD, btnU : in STD_LOGIC; --btnU/D stands for up/down key : out STD_LOGIC_VECTOR (3 downto 0)); end btn_map; architecture Behavioral of btn_map is component trig_4b_Adder is Port ( clk : in STD_LOGIC; --I modified the adder with some D-flops to not create a combinatorial loop (hence the clk) c, y : in STD_LOGIC_VECTOR (3 downto 0); --c/y are the two 4-bit inputs to the adder s : out STD_LOGIC_VECTOR (3 downto 0)); --s = result end component; signal val, add_sub, new_key : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); signal trigger : STD_LOGIC := '0'; -- clock for the adder, "keypressed" begin Adder: trig_4b_Adder port map(clk => trigger, c => val, y => add_sub, s => new_key); -- add_sub is either the +1, -1 or 0 process(btnD, btnU) variable minus : STD_LOGIC_VECTOR (3 downto 0) := "1111"; variable plus : STD_LOGIC_VECTOR (3 downto 0) := "0001"; variable zero : STD_LOGIC_VECTOR (3 downto 0) := "0000"; begin if btnD = '1' then add_sub <= minus; elsif btnU = '1' then add_sub <= plus; else add_sub <= zero; -- (sub zero lol) end if; end process; trigger <= btnU or btnD; -- start the adder val <= new_key; -- I want to save the result from the adder till next clock cycle -- these two lines of code feel bad for some reason, key <= new_key; -- key is the output from this module -- like my design is inherently flawed somehow.. end Behavioral;
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