From the data sheet of ADC it is given that. when cs (chip select) active low ADC start conversion at the rising edge and for subsequent 14 serial clk (falling edge ) it will give 12 bits with two leading zeros and once 14 serial clock (falling edge) completed in the next rising edge the data should be transferred.
I this regard kindly clarify the following question
1. Shall I use rising edge for the total process?
2. whether I should use only falling edge for conversion?
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Ananthan
Hello,
I am trying to interface FPGA and adc..
From the data sheet of ADC it is given that. when cs (chip select) active low ADC start conversion at the rising edge and for subsequent 14 serial clk (falling edge ) it will give 12 bits with two leading zeros and once 14 serial clock (falling edge) completed in the next rising edge the data should be transferred.
I this regard kindly clarify the following question
1. Shall I use rising edge for the total process?
2. whether I should use only falling edge for conversion?
help me!
Thank you
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