PL to PC direct communication

[soha]

I have loaded a Xillinux OS on the Zedboard and I'm currently trying to implement a program trace system in the HW. Specifically, the main idea is to generate traces for objects of interest (i.e. instruction flow) through the Coresight functionality, and download the trace off the FPGA so that I can run some further analysis in my own software environment.
 
AFAIK, traces generated by the 'Coresight' can be exported to custom PL and some analysis/computation can be performed there on-chip. However, this doesn't fit my scenario. So I have two questions,
 
(1) Is there any way that my PL can further offload the trace to an external PC so that I can perform analysis/computation in my own software environment?
 
(2) For my objective described above, is this (i.e. PS --> Coresight trace --> PL --> external PC) the correct way to implement the trace system? Is there any other better option?
 
Thanks.

[D@n]

@soha,

Is there any means of getting the coresight information into the Programming Logic?  If so, how about using a UART to get the communication from there to the PC?

Dan

[soha]

21 minutes ago, D@n said:

@soha,

Is there any means of getting the coresight information into the Programming Logic?  If so, how about using a UART to get the communication from there to the PC?

Dan

2

Hi Dan,

Thanks for your reply. AFAIK, coresight information can be offloaded to the PL through EMIO (I haven't implemented it though. I'm still trying to figure out how the whole system would work).

Regarding UART, I have a question. If I understand correctly, the UART (also ethernet, USB, etc.) can only be accessed through the PS, right? So if I want to set up the communication through UART, the data flow would be PS --> coresight --> PL --> PS --> UART. However, I don't want my trace-offloading functionality to interfere with the PS, instead, I want this function running in parallel with the PS. This is the reason why I'm looking for a way for direct communication between PL and PC. So probably in my case, UART (also ethernet, USB, etc.) may not be an option. Please correct me if I'm wrong. Any more idea? Thanks.

Soha

[D@n]

@soha,

Good catch.  Examining page 6 of the reference manual suggests only PMods would be available for talking to the PC apart from the PS.  Do you have any PMods available to you?  UART PMod?    I suppose you might be able to use some of the other ports, but you might need to do some hardware hackery to get there.  Do you know (yet) how much data this trace would require?

Dan

[soha]

16 minutes ago, D@n said:

@soha,

Good catch.  Examining page 6 of the reference manual suggests only PMods would be available for talking to the PC apart from the PS.  Do you have any PMods available to you?  UART PMod?    I suppose you might be able to use some of the other ports, but you might need to do some hardware hackery to get there.  Do you know (yet) how much data this trace would require?

Dan

 

Hi Dan,

PMod is also what I've found so far from the manual. Another option might be JTAG. Both of them are available now so I think I can use any of them to extract my data. As confirmed by you, probably I would look at PMod first. 

My only concern is the practicality. I'm not sure with the exact number of bytes generated by my tracer before I have a solid implementation but it can be expected to be at KB or MB/s level. So which option do you think would fit my case better, PMod or JTAG? Do I need a FIFO between the connection of the PMod and my PL? Sorry if my question goes too detailed... I'm at evaluation stage and I appreciate your help.  

[D@n]

@soha,

My concern with using the JTAG is whether or not there exists a JTAG controller that will give you access to the coresight info you would like.  ARM should have software for that, since coresight is their chosen debug approach, I just don't know.  If you are trying to get information out of the ZedBoard via a PL approach, and your approach is not going to use a canned ARM provided routine and/or hardware, then ... yeah, I think you would need a PMod.

As for whether or not you would need a FIFO between the PL and the PMod, well ... that depends.  How fast will you be reading this coresight info, and how fast will you be able to dump it out the PMod?  I know I've managed to get the UART on my PC up to 4MBaud, but that's still 250 clocks per byte at a 100MHz clock speed.  Incidentally, you can find a simple usable FIFO here.  As for how big the FIFO needs to be ... well, if you have 32 bytes to send, and you wished to dump them into the FIFO at one byte per clock, you'd need at least 31 positions in your FIFO.  However, the block RAM on any FPGA tends to be limited.  If you've got more information to stuff into the block RAM than you have block RAM on your device, then you'll need your PL to dump this coresight information into the SDRAM on board.

Dan

[soha]

10 minutes ago, D@n said:

@soha,

My concern with using the JTAG is whether or not there exists a JTAG controller that will give you access to the coresight info you would like.  ARM should have software for that, since coresight is their chosen debug approach, I just don't know.  If you are trying to get information out of the ZedBoard via a PL approach, and your approach is not going to use a canned ARM provided routine and/or hardware, then ... yeah, I think you would need a PMod.

As for whether or not you would need a FIFO between the PL and the PMod, well ... that depends.  How fast will you be reading this coresight info, and how fast will you be able to dump it out the PMod?  I know I've managed to get the UART on my PC up to 4MBaud, but that's still 250 clocks per byte at a 100MHz clock speed.  Incidentally, you can find a simple usable FIFO here.  As for how big the FIFO needs to be ... well, if you have 32 bytes to send, and you wished to dump them into the FIFO at one byte per clock, you'd need at least 31 positions in your FIFO.  However, the block RAM on any FPGA tends to be limited.  If you've got more information to stuff into the block RAM than you have block RAM on your device, then you'll need your PL to dump this coresight information into the SDRAM on board.

Dan

 

Hi Dan,

I think I have to start playing with the coresight and PMod and see what's going on. I appreciate all the information and help.