First of all, thanks for providing this forum! I'm just starting out with FPGAs with the Zybo board, which seems a really nifty device, I'm just a little stuck though with the HDMI output example.
I recompiled glibc with the argument in there, which fixed the synthesis crashing issue
When I performed the synthesis and it generated the bitstream, I got the following warning:
[Timing 38-249] Generated clock hdmi_out_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O. [/home/chris/ZYBO/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/ip/hdmi_out_v_tc_0_0/hdmi_out_v_tc_0_0_clocks.xdc:5]
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
I wasn't sure what to do about that warning.
I am using Vivado 2016.4. I was still able to program the Zybo though, but I seem to get no HDMI output, when I attach it to a TV.
I notice I only have /dev/ttyUSB1 on my computer, am I supposed to have two devices, /dev/ttyUSB0 and /dev/ttyUSB1, where usb0, would be used for the uart, and usb1 for jtag?
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anfractuosity
Hey,
First of all, thanks for providing this forum! I'm just starting out with FPGAs with the Zybo board, which seems a really nifty device, I'm just a little stuck though with the HDMI output example.
I would also like to point users of Arch Linux to - https://forums.xilinx.com/t5/Synthesis/Vivado-crashes-on-Arch-Linux-when-performing-synthesis/td-p/706847
I recompiled glibc with the argument in there, which fixed the synthesis crashing issue
When I performed the synthesis and it generated the bitstream, I got the following warning:
[Timing 38-249] Generated clock hdmi_out_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O. [/home/chris/ZYBO/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/ip/hdmi_out_v_tc_0_0/hdmi_out_v_tc_0_0_clocks.xdc:5]
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
I wasn't sure what to do about that warning.
I am using Vivado 2016.4. I was still able to program the Zybo though, but I seem to get no HDMI output, when I attach it to a TV.
I notice I only have /dev/ttyUSB1 on my computer, am I supposed to have two devices, /dev/ttyUSB0 and /dev/ttyUSB1, where usb0, would be used for the uart, and usb1 for jtag?
Just wondering if anyone has any ideas?
Cheers
Chris
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