I want to test the IP core---BRAM,that has true dual ports,portA is 'write first','always enabled',portB is 'read first','always enabled'.Untick the'common clock'.
In the testbench, wea=1,web=0;there are two source clock---clka and clkb that'periods are 8ns respectivly.In addition,
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Sophia_123
Hi,
I want to test the IP core---BRAM,that has true dual ports,portA is 'write first','always enabled',portB is 'read first','always enabled'.Untick the'common clock'.
In the testbench, wea=1,web=0;there are two source clock---clka and clkb that'periods are 8ns respectivly.In addition,
The interface of BRAM is
blk_mem_gen_0 uut(
.clka(clka),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.web(web),
.dinb(),
.addrb(addrb),
.doutb(doutb)
);
for address and data,
#0
wea=1;
web=0;
addra=0;
dina=0;
#10000
addra=1;
dina=2;
#100
addrb=0;
#1000
addrb=1;
#30000
$stop;
In simulate wave,dout is always x. What makes it?
Regards,
Sophia
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