Failed to simulate the BRAM test

[Sophia_123]

Hi,

I want to test the IP core---BRAM,that has true dual ports,portA is 'write first','always enabled',portB is 'read first','always enabled'.Untick the'common clock'. 

In the testbench, wea=1,web=0;there are two source clock---clka and clkb that'periods are 8ns respectivly.In addition,

The interface of BRAM is

blk_mem_gen_0 uut(
.clka(clka),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.web(web),
.dinb(),
.addrb(addrb),
.doutb(doutb) 
);

for address and data,
#0
wea=1;
web=0;
addra=0;
dina=0;
#10000
addra=1;
dina=2;
#100
addrb=0;
#1000
addrb=1; 
#30000
$stop;

In simulate wave,dout is always x. What makes it?

 

 

Regards,

Sophia

[D@n]

@Sophia_123,

I've studied your code this morning and ... I'm not seeing where the X is coming from.  Everything you've got there looks good.  Frankly ... I'm at a loss.  Are you sure you are testing the code you think you are testing?

Dan

[Sophia_123]

@D@n 

You are so  humorous,haha... yes ,I want to use A port as input to write data, and B port as output to read data, so I tried again and again ,but failed again and again...

[D@n]

@Sophia_123,

I wasn't actually joking.

I remember once, years ago, working with a partner who was struggling to get some code working.  He'd make changes--obvious ones like printf("I am here");--and recompile and nothing would change.  He'd then undo those changes, try something else, and the code would now print "I am here."  This created quite the frustrating evening, until we realized that he was editing on one computer, building on another, and the files were stored on a third computer/file server.  Once he switched to editing and building on the same computer, the strangeness went away.

I've had the problem with Vivado as well.  Once I set the flag to copy my sources into my project, built it, didn't like it, edited the sources and none of my changes took.  I made more changes--no difference.  More changes, no difference.  It wasn't until sometime later that I discovered Vivado had copied my files into another directory that it was then using to build from.

So ... I'm just asking, it might not be your problem--but it's worth double checking.

Dan

[Sophia_123]

@D@n,

I tried again, but the result is so frustrating.

 

I can't agree you more.I think I can try it in another version of Vivado...

 

Sophia

[D@n]

@Sophia_123,

Wait ... did that last version work? You wrote to address zero a zero.  You read zero from that address.  You then dropped WEA, and so didn't write to any other addresses and thus nothing can be expected from reading from other addresses.  This is what your test shows, is it not?

Dan

[Sophia_123]

@D@n

I tested it in the last version,but failed again. In the last wave as it shows , I lifted the WEA  at second period, and dropped the WEB. Then I  wrote datas to sequent addresses. at the same time readed from B port.  However, the data from B is also zero. 

That's my testbench.

`timescale 1ns / 1ps

module test_bram;

    // Inputs
    reg clka;
    reg [0:0] wea;
    reg[0:0] rsta;
    reg [3:0] addra;
    reg [15:0] dina;
    reg clkb;
    reg [0:0] web;
    reg [3:0] addrb;

    // Outputs
    wire [15:0] doutb;

    // Instantiate the Unit Under Test (UUT)
    blk_mem_gen_0 uut (
        .clka(clka), 
        .rsta(rsta),
        .wea(wea), 
        .addra(addra), 
        .dina(dina), 
        .douta(), 
        .clkb(clkb), 
        .web(web), 
        .addrb(addrb), 
        .dinb(), 
        .doutb(doutb)
    );
    
    initial begin
            clkb = 0;
            forever #4 clkb=~clkb;        
            end
                initial begin
            clka = 0;
            forever #4 clka=~clka;        
            end

    initial begin
        // Initialize Inputs
        #0
        rsta=1;
        wea = 0;
        addra = 1;
        dina = 1;        
        web = 0;
        addrb = 1;
        // Wait 100 ns for global reset to finish
        #8
        rsta=0;
        wea=1;
        addra=2;
        dina=2;
        addrb=2;
        #8
        addra=3;
        dina=4;
        addrb=3;
        #8
        $stop;

    end      
endmodule

 

[D@n]

@Sophia_123,

Try this for now .... just to know things are working:  Hold WEA high until you've set every memory address you are going to try reading.  And two, read B one cycle after setting A.  (I think your eventual goal is to read them on the same clock, but for now let's just check if the memory works--we'll check misconfiguration next).

Dan

[Sophia_123]

@D@n

I made a fool mistake...I didn't make the B port enable...I thought I set it 'always enable'. I think I need more carefulness.Thanks for your help very much!